Abstract: Low-density parity-check (LDPC) coding based on memory cell voltage distribution (CVD) in data storage devices. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory; and a controller. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory, and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages, and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.

Abstract: Technology for two-sided adjacent memory cell interference mitigation in a non-volatile storage system is disclosed. During reading of target memory cells, the storage system applies a suitable magnitude read pass voltage to a first unselected word line adjacent to a target word line to compensate for interference from adjacent cells on the first unselected word line while applying a suitable magnitude read reference voltage to the target word line to compensate for interference from adjacent cells on a second unselected word line on the other side of the target word line. The read pass voltage may compensate for interference due to charge being added to when programming cells on the first unselected word line after programming the target cells. The read reference voltage may compensate for interference due to charge movement near the target cells that results from charge stored in the cells on the second unselected word line.

Abstract: A storage apparatus includes non-volatile memory cells formed on a memory die, each memory cell configured to hold bits of data, and a control circuit formed on the memory die. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read the memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data. In some cases, the recovered data may have a high bit error rate. To handle higher bit error rates, the use of soft bit data is incorporated into an encoded foggy-fine scheme.

Abstract: A storage system has a memory with memory cells that can store a non-power-of-two number of states. A map is used to distribute data bits in the memory. The map can be a modified version of a quadrature amplitude modulation (QAM) map. The mapping can be done by a controller in the storage system or by the memory die. Performing the mapping in the memory die can reduce data traffic between the controller and the memory die, which can provide an improvement to performance and power consumption.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a read threshold on a wordline, adjust a read threshold voltage level associated with the read threshold, determine an adjusted read threshold at the adjusted read threshold voltage level, where the adjusted read threshold is different from the read threshold, compare the adjusted read threshold to the read threshold, and calibrate the read threshold based on the comparing. The controller is further configured to analyze a bit error rate (BER) difference based on the calibrating and/or a previous read threshold voltage level movement, choose a next target read threshold for next calibration, and read a second page at the next target read threshold.

Abstract: A data storage device includes a hard disk drive coupled to a printed circuit board (PCB), a volatile memory device coupled to the PCB, a non-volatile memory device coupled to the PCB, and a controller coupled to the PCB, such that the controller is in communication with the hard disk drive, the volatile memory device, and the non-volatile memory device. The controller is configured to identify patterns and/or structures of metadata for the hard disk drive, perform one or more of the following to the metadata to tailor the metadata: data shaping, content aware decoding, adaptive data trimming, and/or adaptive metablock sizing, and write the tailored metadata to the non-volatile memory device. The metadata is at least one of repeatable run out metadata, positioning error signal metadata, adjacent track interference metadata, and/or emergency power off metadata.

Abstract: Interleaved ECC coding for key-value data storage devices. In one embodiment, a controller includes a memory interface including a namespace database; an ECC engine; a controller memory; and an electronic processor. The electronic processor is configured to receive a host write command, determine whether write access was setup as a key-value (KV) namespace in the namespace database and is associated with the host write command, and control the ECC engine and the memory interface to perform one or more program operations on the data in the memory using the interleaved ECC coding and based on the host write command in response to determining that the write access was setup as the KV namespace in the namespace database and the KV namespace is associated with the host write command.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.

Abstract: A method and apparatus for determining the sector size and concomitant host metadata size to determine the difference between total size of the data block to be stored, and using the difference for parity data. This allows an increase in parity bits available for smaller sector sizes and/or data with smaller host metadata sizes. Because the amount of space available for additional parity bits is known, data with lower numbers of parity bits may be assigned to higher quality portions a memory array written with longer programming trim times, and/or written to memory dies with good redundant columns, further increasing performance and reliability.

Abstract: A method and apparatus for calibrating read threshold for cells of a target wordline (WL) that may be conducted on a die, in a controller connected to a memory die, or both. Voltage values of one or more adjacent WL cells are read, and based on the voltage values of the adjacent cells, cells of the target WL are grouped. A read threshold calibration is carried out on each group. The calibration thresholds are then used for read operations on the cells of each distinct group of the target WL.

Abstract: Calibration of soft bit reference levels in a non-volatile memory system is disclosed. When the soft bit reference levels are to be calibrated, encoded data is read from a group of the memory cells. The encoded data is decoded and error corrected. Therefore, the original data that was programmed into the memory cells is recovered. The group of memory cells are sensed at candidate soft bit reference levels, and possibly other reference levels. For each candidate soft bit reference level, mutual information between the original programmed data and the data for that candidate soft bit reference level is determined. The mutual information serves as a good measure for how well the candidate soft bit reference level will aid in decoding the data. In an aspect, a soft bit reference level having the highest mutual information out of several candidates is selected as the calibrated soft bit reference level.

Abstract: A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.

Abstract: Calibration of soft bit reference levels in a non-volatile memory system is disclosed. When the soft bit reference levels are to be calibrated, encoded data is read from a group of the memory cells. The encoded data is decoded and error corrected. Therefore, the original data that was programmed into the memory cells is recovered. The group of memory cells are sensed at candidate soft bit reference levels, and possibly other reference levels. For each candidate soft bit reference level, mutual information between the original programmed data and the data for that candidate soft bit reference level is determined. The mutual information serves as a good measure for how well the candidate soft bit reference level will aid in decoding the data. In an aspect, a soft bit reference level having the highest mutual information out of several candidates is selected as the calibrated soft bit reference level.

Abstract: A storage circuit is configured to store multiple vectors associated with variable and check nodes of an iterative decoding operation. As part of the iterative decoding operation, a processor circuit is configured to retrieve, from the storage circuit, an intermediate value vector, a first estimation vector, a second estimation vector, and a sign vector, and determine an absolute value of the intermediate value vector. The processor circuit is also configured, using the retrieved vectors, to generate updated values for the first and second estimation vectors as part of determining a bit estimate for a check node included in the iterative decoding operation.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create a dual parity matrix. The dual parity matrix includes a full parity form that includes a payload, a first parity portion, and a second parity portion and a reduced parity form that includes the payload and the first parity portion. The second parity portion is 0. The controller is further configured to create an incremental parity construction matrix. The incremental parity construction matrix includes two arrays. A first array includes a first payload portion, a first, first parity portion, and a first, second parity portion and a second array includes a second payload portion, a second, first parity portion, and a second, second parity portion. The incremental parity construction matrix is arranged in either a block triangular construction or a block diagonal construction.

Abstract: A memory controller includes, in one embodiment, a memory interface, a plurality of decoders, and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. Each decoder of the plurality of decoders is configured to determine a bit error rate (BER). The controller circuit configured to generate a plurality of bit-error-rate estimation scan (BES) hypotheses for one wordline of the plurality of wordlines, divide the plurality of BES hypotheses among the plurality of decoders, receive BER results from the plurality of decoders based on the plurality of BES hypotheses, and adjust one or more read locations of the one wordline based on the BER results from the plurality of decoders.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.

Abstract: A storage apparatus includes non-volatile memory cells formed on a memory die, each memory cell configured to hold bits of data, and a control circuit. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data. To improve the accuracy of recovering the encoded foggy phase data, techniques are presented to calibrate the voltage levels used in sensing the foggy state distributions.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.

Abstract: A read threshold voltage can vary over time due to process variation, data retention issues, and program disturb conditions. A storage system can calibrate the read threshold voltage using data from a decoded codeword read from a wordline in the memory. For example, the storage system can use the data instead of syndrome weight in a bit error rate estimate scan (BES). As another example, the storage system can use the data to generate a bit error rate distribution, which can be used instead of a cell voltage distribution histogram. Using these techniques can help reduce latency and power consumption, increase throughput, and improve quality of service.