Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

Abstract: Creating by a computer an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In accordance with aspects of the present disclosure, a computer-implemented method for statistical static timing analysis of an integrated circuit is provided. The method may comprise identifying a timing parameter that contributes to a delay calculation. The method may further comprise determining, by a processing device, whether the identified timing parameter significantly impacts the delay calculation. The method may also comprise, responsive to determining that the identified timing parameter does not significantly impact the delay calculation, avoiding a sensitivity calculation for the identified timing parameter.

Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.

Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.

Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.

Abstract: In an approach for addressing process and voltage points across voltage and process space, a computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies a minimum set of voltage/process pairs associated with the integrated circuit design. The computer identifies a number n that defines the number of finite differencing operations to be performed for the identified minimum set of voltage/process pairs. The computer performs a single statistical static timing analysis with multi-corner projection for the identified integrated circuit based on the received number n that provides a finite difference for each number of finite differencing operations to be performed based on n for the identified minimum set of voltage/process pairs. The computer performs addressing based on the performed statistical static timing analysis. The computer provides a report.

Abstract: According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.

Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

Abstract: A design and timing model for at least one circuit path of at least a portion of an IC design is loaded into a computer. At least one canonical clock variable associated with the model is defined; it includes at least one source of variation. The computer is used to perform an SSTA of the at least one circuit path, based on the design and timing model and the at least one canonical clock variable, to obtain slack canonical data. A clock period is projected, based on the slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical. Results of the SSTA and the projected clock period are output to determine performance compliance. Efficient operation of the computer is enhanced by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In accordance with aspects of the present disclosure, a computer-implemented method for statistical static timing analysis of an integrated circuit is provided. The method may comprise identifying a timing parameter that contributes to a delay calculation. The method may further comprise determining, by a processing device, whether the identified timing parameter significantly impacts the delay calculation. The method may also comprise, responsive to determining that the identified timing parameter does not significantly impact the delay calculation, avoiding a sensitivity calculation for the identified timing parameter.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Statistically modeling timing in a digital circuit through the use of canonical form models, where some terms of the form represent sources of variation sensitive to only a subset of timing regions of the circuit. When propagating the form through regions through which some set of terms in the model is not sensitive, those terms are collapsed by placing them in a cache and replacing them in the form with a single combined term that references the cached terms.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Abstract: Various embodiments include approaches for analyzing a set of travel pathways for a priority vehicle. In some cases, an approach includes: obtaining data indicating a location of the priority vehicle and a location of a destination for the priority vehicle; ranking each of a set of paths between the location of the priority vehicle and the location of the destination based upon a travel time for the priority vehicle along the set of paths; and sending instructions to vehicles on a highest-ranked path in the set of paths to initiate providing a right-of-way to the priority vehicle, wherein vehicles closer to the destination along the highest-ranked path are instructed to change a corresponding position prior to vehicles farther from the destination along the highest-ranked path.