Patents by Inventor Eric R. Miller

Eric R. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151444
    Abstract: A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.
    Type: Application
    Filed: January 9, 2025
    Publication date: May 8, 2025
    Inventors: David J. Gulbransen, Sean P. Kilcoyne, Eric R. Miller, Matthew D. Chambers, Eric J. Beuville, Andrew E. Gin, Adam M. Kennedy
  • Publication number: 20250142856
    Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
    Type: Application
    Filed: November 1, 2024
    Publication date: May 1, 2025
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 12166110
    Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: December 10, 2024
    Assignee: Adeia Semiconductor Solutions LLC
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 12148721
    Abstract: Interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: November 19, 2024
    Assignee: RAYTHEON COMPANY
    Inventors: Eric R. Miller, Sean P. Kilcoyne, Michael V. Liguori, Michael J. Rondon
  • Publication number: 20240158368
    Abstract: Pyrrolidine main protease inhibitors are described that are effective as antiviral compounds.
    Type: Application
    Filed: October 12, 2023
    Publication date: May 16, 2024
    Applicant: AbbVie Inc.
    Inventors: David A. Degoey, Michael R. Schrimpf, David J. Hardee, Jacob Ludwig, Eric R. Miller, Timothy R. Hodges, Alberto Munoz, Sarah J. Perlmutter, Huan-Qiu X. Li, Alvin Jang, Elizabeth L. Noey, Gregory A. Gfesser, Edgars Jecs, Robert G. Schmidt, Justin D. Dietrich, Xenia B. Searle, Boguslaw P. Nocek, Andrew Bogdan
  • Patent number: 11975539
    Abstract: A marking system includes a valve body including an orifice plate including multiple orifices and multiple micro-valves. Each micro-valve includes an actuating beam movable from a closed position in which a corresponding one of the orifices is sealed by a portion of the actuating beam such that the micro-valve is closed, into a peak position in response to application of a control signal. A controller is configured to generate a control signal for each of the actuating beams, each control signal including a drive pulse having a predetermined voltage such that the actuating beam moves from the closed position into the peak position in which the corresponding orifice is open and returns to the closed position in a characteristic period, wherein the drive pulse has a duration that substantially corresponds to the characteristic period such that the actuating beam is in the closed position after the drive pulse is complete.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: May 7, 2024
    Assignee: Matthews International Corporation
    Inventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Ken Trueba, Jeff Hess
  • Publication number: 20240120242
    Abstract: An integrated circuit wafer is produced to include a substrate comprising a conductive layer and an insulating layer. The wafer can further be produced to include one or more circuit TSVs formed at least partially through the substrate and associated with an integrated circuit (IC). A test structure configured to facilitate testing of the integrity of the one or more circuit TSVs can be formed on the wafer. The test structure can include a first test TSV formed one of partially through the insulating layer, or through the insulating layer and partially through the conductive layer of the substrate, and a second test TSV formed one of partially through the insulating layer, or through the insulating layer and partially through the conductive layer of the substrate. The first test TSV and the second test TSV can operate as witness TSVs to the operability of the circuit TSVs.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: Sean P. Kilcoyne, Eric R. Miller
  • Patent number: 11938733
    Abstract: A micro-valve includes an orifice plate having a first surface, a second surface and an orifice extending from the first surface to the second surface. An actuating beam is disposed in spaced relation to the orifice plate. The actuating beam includes a base portion and a cantilevered portion. The base portion is separated from the orifice plate by a predetermined distance. The cantilevered portion extends from the base portion such that an overlapping portion thereof overlaps the orifice. The actuating beam is movable between a closed position and an open position. The micro-valve also includes a sealing structure including a sealing member disposed at the overlapping portion of the cantilevered portion. When the actuating beam is in the closed position, the cantilevered portion is positioned such that the sealing structure seals the orifice so as to close the micro-valve.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: March 26, 2024
    Assignee: Matthews International Corporation
    Inventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Glenn J. T. Leighton
  • Publication number: 20240088268
    Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
    Type: Application
    Filed: April 12, 2023
    Publication date: March 14, 2024
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Publication number: 20240034058
    Abstract: A marking system includes a valve body including an orifice plate including multiple orifices and multiple micro-valves. Each micro-valve includes an actuating beam movable from a closed position in which a corresponding one of the orifices is sealed by a portion of the actuating beam such that the micro-valve is closed, into a peak position in response to application of a control signal. A controller is configured to generate a control signal for each of the actuating beams, each control signal including a drive pulse having a predetermined voltage such that the actuating beam moves from the closed position into the peak position in which the corresponding orifice is open and returns to the closed position in a characteristic period, wherein the drive pulse has a duration that substantially corresponds to the characteristic period such that the actuating beam is in the closed position after the drive pulse is complete.
    Type: Application
    Filed: May 26, 2023
    Publication date: February 1, 2024
    Inventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Ken Trueba, Jeff Hess
  • Publication number: 20240018684
    Abstract: A wafer stack can be produced by using indium electroplating on physical vapor deposition tantalum. The wafer stack includes a substrate, a tantalum-nitride film formed on the substrate, a tantalum layer formed on the tantalum-nitride film, and indium deposited on the tantalum layer. Various relationships of thicknesses between the tantalum layer and the tantalum-nitride film can be used in producing the wafer stack.
    Type: Application
    Filed: August 2, 2023
    Publication date: January 18, 2024
    Inventors: Michael J. Rondon, Jon Sigurdson, Eric R. Miller
  • Patent number: 11869936
    Abstract: A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.
    Type: Grant
    Filed: August 14, 2021
    Date of Patent: January 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Marc Adam Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
  • Patent number: 11869937
    Abstract: A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: January 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Marc Adam Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
  • Publication number: 20230352480
    Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.
    Type: Application
    Filed: December 1, 2022
    Publication date: November 2, 2023
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 11794476
    Abstract: A micro-valve includes an orifice plate including a first surface and a second surface, and an orifice extending from the first surface to the second surface. The micro-valve also includes a spacing member disposed on the first surface and offset from the orifice, a valve seat disposed on the first surface. The valve seat defines an opening in fluid communication with the orifice in a flow direction. The micro-valve also includes an actuating beam disposed on the spacing member extending from the spacing member toward the orifice, the actuating beam being moveable between an open position and a closed position. The micro-valve also includes a sealing member affixed to an end portion of the actuating beam. In a closed position, a sealing surface of the sealing member contacts the valve seat to close the micro-valve.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 24, 2023
    Assignee: Matthews International Corporation
    Inventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Glenn J. T. Leighton
  • Publication number: 20230294399
    Abstract: A micro-valve includes an orifice plate having a first surface, a second surface and an orifice extending from the first surface to the second surface. An actuating beam is disposed in spaced relation to the orifice plate. The actuating beam includes a base portion and a cantilevered portion. The base portion is separated from the orifice plate by a predetermined distance. The cantilevered portion extends from the base portion such that an overlapping portion thereof overlaps the orifice. The actuating beam is movable between a closed position and an open position. The micro-valve also includes a sealing structure including a sealing member disposed at the overlapping portion of the cantilevered portion. When the actuating beam is in the closed position, the cantilevered portion is positioned such that the sealing structure seals the orifice so as to close the micro-valve.
    Type: Application
    Filed: October 24, 2022
    Publication date: September 21, 2023
    Inventors: William A. BUSKIRK, Steven E. FLEGO, Charles C. HALUZAK, John WHITLOCK, Eric R. MILLER, Glenn J.T. LEIGHTON
  • Patent number: 11753736
    Abstract: A method for fabricating a wafer stack. The method includes forming a tantalum-nitride film on a substrate of the wafer stack using physical vapor deposition, forming a tantalum layer on the tantalum-nitride film using physical vapor deposition, and depositing indium on the tantalum layer using electroplating.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: September 12, 2023
    Assignee: RAYTHEON COMPANY
    Inventors: Michael J. Rondon, Jon Sigurdson, Eric R. Miller
  • Patent number: 11710756
    Abstract: A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: July 25, 2023
    Assignee: RAYTHEON COMPANY
    Inventors: Jamal I. Mustafa, Robert C. Anderson, John L. Vampola, Sean P. Kilcoyne, Eric R. Miller, George Grama
  • Patent number: 11660861
    Abstract: A marking system includes a valve body including an orifice plate including multiple orifices and multiple micro-valves. Each micro-valve includes an actuating beam movable from a closed position in which a corresponding one of the orifices is sealed by a portion of the actuating beam such that the micro-valve is closed, into a peak position in response to application of a control signal. A controller is configured to generate a control signal for each of the actuating beams, each control signal including a drive pulse having a predetermined voltage such that the actuating beam moves from the closed position into the peak position in which the corresponding orifice is open and returns to the closed position in a characteristic period, wherein the drive pulse has a duration that substantially corresponds to the characteristic period such that the actuating beam is in the closed position after the drive pulse is complete.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: May 30, 2023
    Assignee: Matthews International Corporation
    Inventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Ken Trueba, Jeff Hess
  • Patent number: 11652161
    Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: May 16, 2023
    Assignee: Tessera LLC
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan