Patents by Inventor Eric R. Miller
Eric R. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120242Abstract: An integrated circuit wafer is produced to include a substrate comprising a conductive layer and an insulating layer. The wafer can further be produced to include one or more circuit TSVs formed at least partially through the substrate and associated with an integrated circuit (IC). A test structure configured to facilitate testing of the integrity of the one or more circuit TSVs can be formed on the wafer. The test structure can include a first test TSV formed one of partially through the insulating layer, or through the insulating layer and partially through the conductive layer of the substrate, and a second test TSV formed one of partially through the insulating layer, or through the insulating layer and partially through the conductive layer of the substrate. The first test TSV and the second test TSV can operate as witness TSVs to the operability of the circuit TSVs.Type: ApplicationFiled: October 11, 2022Publication date: April 11, 2024Inventors: Sean P. Kilcoyne, Eric R. Miller
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Patent number: 11938733Abstract: A micro-valve includes an orifice plate having a first surface, a second surface and an orifice extending from the first surface to the second surface. An actuating beam is disposed in spaced relation to the orifice plate. The actuating beam includes a base portion and a cantilevered portion. The base portion is separated from the orifice plate by a predetermined distance. The cantilevered portion extends from the base portion such that an overlapping portion thereof overlaps the orifice. The actuating beam is movable between a closed position and an open position. The micro-valve also includes a sealing structure including a sealing member disposed at the overlapping portion of the cantilevered portion. When the actuating beam is in the closed position, the cantilevered portion is positioned such that the sealing structure seals the orifice so as to close the micro-valve.Type: GrantFiled: October 24, 2022Date of Patent: March 26, 2024Assignee: Matthews International CorporationInventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Glenn J. T. Leighton
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Publication number: 20240088268Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.Type: ApplicationFiled: April 12, 2023Publication date: March 14, 2024Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
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Publication number: 20240034058Abstract: A marking system includes a valve body including an orifice plate including multiple orifices and multiple micro-valves. Each micro-valve includes an actuating beam movable from a closed position in which a corresponding one of the orifices is sealed by a portion of the actuating beam such that the micro-valve is closed, into a peak position in response to application of a control signal. A controller is configured to generate a control signal for each of the actuating beams, each control signal including a drive pulse having a predetermined voltage such that the actuating beam moves from the closed position into the peak position in which the corresponding orifice is open and returns to the closed position in a characteristic period, wherein the drive pulse has a duration that substantially corresponds to the characteristic period such that the actuating beam is in the closed position after the drive pulse is complete.Type: ApplicationFiled: May 26, 2023Publication date: February 1, 2024Inventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Ken Trueba, Jeff Hess
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Publication number: 20240018684Abstract: A wafer stack can be produced by using indium electroplating on physical vapor deposition tantalum. The wafer stack includes a substrate, a tantalum-nitride film formed on the substrate, a tantalum layer formed on the tantalum-nitride film, and indium deposited on the tantalum layer. Various relationships of thicknesses between the tantalum layer and the tantalum-nitride film can be used in producing the wafer stack.Type: ApplicationFiled: August 2, 2023Publication date: January 18, 2024Inventors: Michael J. Rondon, Jon Sigurdson, Eric R. Miller
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Patent number: 11869937Abstract: A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.Type: GrantFiled: January 19, 2022Date of Patent: January 9, 2024Assignee: International Business Machines CorporationInventors: Marc Adam Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
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Patent number: 11869936Abstract: A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.Type: GrantFiled: August 14, 2021Date of Patent: January 9, 2024Assignee: International Business Machines CorporationInventors: Marc Adam Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
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Publication number: 20230352480Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.Type: ApplicationFiled: December 1, 2022Publication date: November 2, 2023Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
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Patent number: 11794476Abstract: A micro-valve includes an orifice plate including a first surface and a second surface, and an orifice extending from the first surface to the second surface. The micro-valve also includes a spacing member disposed on the first surface and offset from the orifice, a valve seat disposed on the first surface. The valve seat defines an opening in fluid communication with the orifice in a flow direction. The micro-valve also includes an actuating beam disposed on the spacing member extending from the spacing member toward the orifice, the actuating beam being moveable between an open position and a closed position. The micro-valve also includes a sealing member affixed to an end portion of the actuating beam. In a closed position, a sealing surface of the sealing member contacts the valve seat to close the micro-valve.Type: GrantFiled: May 9, 2019Date of Patent: October 24, 2023Assignee: Matthews International CorporationInventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Glenn J. T. Leighton
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Publication number: 20230294399Abstract: A micro-valve includes an orifice plate having a first surface, a second surface and an orifice extending from the first surface to the second surface. An actuating beam is disposed in spaced relation to the orifice plate. The actuating beam includes a base portion and a cantilevered portion. The base portion is separated from the orifice plate by a predetermined distance. The cantilevered portion extends from the base portion such that an overlapping portion thereof overlaps the orifice. The actuating beam is movable between a closed position and an open position. The micro-valve also includes a sealing structure including a sealing member disposed at the overlapping portion of the cantilevered portion. When the actuating beam is in the closed position, the cantilevered portion is positioned such that the sealing structure seals the orifice so as to close the micro-valve.Type: ApplicationFiled: October 24, 2022Publication date: September 21, 2023Inventors: William A. BUSKIRK, Steven E. FLEGO, Charles C. HALUZAK, John WHITLOCK, Eric R. MILLER, Glenn J.T. LEIGHTON
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Patent number: 11753736Abstract: A method for fabricating a wafer stack. The method includes forming a tantalum-nitride film on a substrate of the wafer stack using physical vapor deposition, forming a tantalum layer on the tantalum-nitride film using physical vapor deposition, and depositing indium on the tantalum layer using electroplating.Type: GrantFiled: November 16, 2020Date of Patent: September 12, 2023Assignee: RAYTHEON COMPANYInventors: Michael J. Rondon, Jon Sigurdson, Eric R. Miller
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Patent number: 11710756Abstract: A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.Type: GrantFiled: November 19, 2020Date of Patent: July 25, 2023Assignee: RAYTHEON COMPANYInventors: Jamal I. Mustafa, Robert C. Anderson, John L. Vampola, Sean P. Kilcoyne, Eric R. Miller, George Grama
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Patent number: 11660861Abstract: A marking system includes a valve body including an orifice plate including multiple orifices and multiple micro-valves. Each micro-valve includes an actuating beam movable from a closed position in which a corresponding one of the orifices is sealed by a portion of the actuating beam such that the micro-valve is closed, into a peak position in response to application of a control signal. A controller is configured to generate a control signal for each of the actuating beams, each control signal including a drive pulse having a predetermined voltage such that the actuating beam moves from the closed position into the peak position in which the corresponding orifice is open and returns to the closed position in a characteristic period, wherein the drive pulse has a duration that substantially corresponds to the characteristic period such that the actuating beam is in the closed position after the drive pulse is complete.Type: GrantFiled: April 30, 2021Date of Patent: May 30, 2023Assignee: Matthews International CorporationInventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Ken Trueba, Jeff Hess
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Patent number: 11652161Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.Type: GrantFiled: June 11, 2021Date of Patent: May 16, 2023Assignee: Tessera LLCInventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
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Patent number: 11639057Abstract: A method of constructing a micro-valve includes providing a substrate for an actuating beam of the micro-valve, the substrate including a first surface and a second surface. The method also includes forming a plurality of constituent layers on the first surface of the actuating beam, including a layer of piezoelectric material. The method also includes removing a portion of the substrate from at least one of the first surface or the second surface to define a cantilevered portion of the actuating beam. The method also includes providing an orifice plate including an orifice. The method also includes providing a valve seat on a surface of the orifice plate, the valve seat having an opening aligned with the orifice. The method also includes attaching the surface of the orifice plate to the second surface via an adhesive such that an overlapping portion of the cantilevered portion overlaps the orifice.Type: GrantFiled: May 9, 2019Date of Patent: May 2, 2023Assignee: Matthews International CorporationInventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Glenn J. T. Leighton
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Patent number: 11557589Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.Type: GrantFiled: March 30, 2020Date of Patent: January 17, 2023Assignee: Tessera, LLCInventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
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Publication number: 20220359437Abstract: Interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.Type: ApplicationFiled: July 22, 2022Publication date: November 10, 2022Inventors: Eric R. Miller, Sean P. Kilcoyne, Michael V. Liguori, Michael J. Rondon
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Patent number: 11479041Abstract: A micro-valve includes an orifice plate having a first surface, a second surface and an orifice extending from the first surface to the second surface. An actuating beam is disposed in spaced relation to the orifice plate. The actuating beam includes a base portion and a cantilevered portion. The base portion is separated from the orifice plate by a predetermined distance. The cantilevered portion extends from the base portion such that an overlapping portion thereof overlaps the orifice. The actuating beam is movable between a closed position and an open position. The micro-valve also includes a sealing structure including a sealing member disposed at the overlapping portion of the cantilevered portion. When the actuating beam is in the closed position, the cantilevered portion is positioned such that the sealing structure seals the orifice so as to close the micro-valve.Type: GrantFiled: May 9, 2019Date of Patent: October 25, 2022Assignee: Matthews International CorporationInventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Glenn J. T. Leighton
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Patent number: 11430753Abstract: Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.Type: GrantFiled: July 8, 2020Date of Patent: August 30, 2022Assignee: RAYTHEON COMPANYInventors: Eric R. Miller, Sean P. Kilcoyne, Michael V. Liguori, Michael J. Rondon
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Publication number: 20220219455Abstract: A micro-valve includes an orifice plate including an orifice. The micro-valve further includes an actuating beam having a first end and a second end. The actuating beam also includes a base layer and a layer of piezoelectric material disposed on the base layer, a bottom electrode layer, and a top electrode layer. At an electrical connection portion of the actuating beam, the layer of piezoelectric material includes a first via, and a portion of the top electrode layer disposed within the first via, and a portion of the bottom electrode disposed beneath the first via. The actuating beam includes a base portion extending from the electrical connection portion and a cantilevered portion extending from the base portion. The cantilevered portion is movable in response to application of a differential electrical signal between the bottom electrode layer and the top electrode layer to one of open or close the micro-valve.Type: ApplicationFiled: November 29, 2021Publication date: July 14, 2022Inventors: William A. Buskirk, Steven E. Flego, Charles C. Haluzak, John Whitlock, Eric R. Miller, Glenn J.T. Leighton, Charles Gilson