Patents by Inventor Eric R. Miller

Eric R. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10931848
    Abstract: A printed document client receives a first print stream for a soft copy document, determines whether one or more conditions for adding a graphical symbol to the printed document are satisfied, and when the one or more conditions for adding the graphical symbol to the printed document are satisfied, adds the graphical symbol to the first print stream to generate a second print stream that includes the graphical symbol, and outputs the second print stream to a printer so the graphical symbol is printed on the printed document corresponding to the soft copy document. The printed document can be a hard copy document or a soft copy document generated from the second print stream.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: February 23, 2021
    Assignee: DocSolid LLC
    Inventors: Steven W. Irons, David R. Guilbault, Eric R. Lynn, Dale Shoup, Anthony Argenziano, Simon Okunev, Ian M. Miller
  • Patent number: 10886271
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Fee Li Lie, Eric R. Miller, Sean Teehan
  • Patent number: 10885002
    Abstract: A recipe management system includes a versioning system that tracks the revision history of templates and their child instances. Modifications to templates and instances create new records with new primary key identifiers and version identifiers. However, each new version of a template or instance has the same root identifier as the prior versions. When a template is modified, a flag is set in its child instances, but they are not modified automatically. When an instance is modified, it has no effect on the parent template. At runtime, a recipe model is loaded to an equipment model to execute a recipe on a piece of equipment. Only approved versions of equipment models are used during execution, even if newer versions exist. During execution, new equipment models can be created. The recipe management system includes an execution engine that can be hosted as a standalone executable or in a system platform.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: January 5, 2021
    Assignee: AVEVA SOFTWARE, LLC
    Inventors: Eric P. Grove, Donald R. Tunnell, Jr., Christopher Justin Miller
  • Patent number: 10833190
    Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10818663
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: October 27, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Fee Li Lie, Eric R. Miller, Sean Teehan
  • Publication number: 20200333401
    Abstract: In accordance with at least selected embodiments, the present disclosure or invention is directed to novel or improved testing apparatus for testing lead acid batteries and/or their components, and/or the efficacy of their components, testing tables, testing systems, and/or related methods. In accordance with at least certain embodiments, the present disclosure or invention is directed to novel or improved methods for testing lead acid batteries and/or their components, and/or the efficacy of their components. In accordance with at least certain selected embodiments, the present disclosure or invention is directed to novel or improved systems for testing lead acid batteries and/or their components, and/or the efficacy of their components.
    Type: Application
    Filed: September 28, 2018
    Publication date: October 22, 2020
    Inventors: Eric H. Miller, James P. Perry, Nicholas R. Shelton, Gregory L. Hall
  • Publication number: 20200325704
    Abstract: A dead bolt lock system including a slider member operatively coupled to a dead bolt such that when the slider member is in a first position, the dead bolt is in an extended position. When the slider member is in a second position, the dead bolt is in the retracted position. The system also includes a first movable member positioned in a path of movement of the slider member and configured to be displaced by the slider member to allow the slider member to move to the second position. The system includes a first lock having a first condition preventing the displacement of the first movable member and a second condition allowing the displacement of the first movable member, a second lock having a first condition preventing the displacement of the first movable member and a second condition allowing the displacement of the first movable member.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: J. Clayton Miller, Eric C. Elkins, Michael S. Yacobi, Edmund P. Deja, Lynn D. Damron, Danny R Maynard
  • Publication number: 20200321580
    Abstract: Disclosed herein are improved separators for lead acid batteries, improved batteries, and related methods. The separators may include a porous membrane, rubber and/or latex, and at least one performance enhancing additive or surfactant.
    Type: Application
    Filed: June 1, 2017
    Publication date: October 8, 2020
    Inventors: James Paul PERRY, Ahila Krishnamoorthy, Kumar Manickam, Susmitha Appikatla, M. Neal Golovin, Eric H. Miller, Margaret R. Roberts
  • Patent number: 10790393
    Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew M. Greene, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Eric R. Miller, Pietro Montanini
  • Patent number: 10760302
    Abstract: A dead bolt lock system including a slider member operatively coupled to a dead bolt such that when the slider member is in a first position, the dead bolt is in an extended position. When the slider member is in a second position, the dead bolt is in the retracted position. The system also includes a first movable member positioned in a path of movement of the slider member and configured to be displaced by the slider member to allow the slider member to move to the second position. The system includes a first lock having a first condition preventing the displacement of the first movable member and a second condition allowing the displacement of the first movable member, a second lock having a first condition preventing the displacement of the first movable member and a second condition allowing the displacement of the first movable member.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: September 1, 2020
    Assignee: Lockmasters Technologies Inc.
    Inventors: J. Clayton Miller, Eric C. Elkins, Michael S. Yacobi, Edmund P. Deja, Lynn D. Damron, Danny R Maynard
  • Publication number: 20200262852
    Abstract: The present disclosure relates to (a) carbidopa prodrugs, (b) pharmaceutical combinations and compositions comprising a carbidopa prodrug and/or an L-dopa prodrug, and (c) methods of treating Parkinson's disease and associated conditions comprising administering a carbidopa prodrug and an L-dopa prodrug to a subject with Parkinson's disease.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Inventors: Benoit Cardinal-David, Vincent S. Chan, Kassibla E. Dempah, Brian P. Enright, Rodger F. Henry, Raimundo Ho, Ye Huang, Alexander D. Huters, Russell C. Klix, Scott W. Krabbe, Philip R. Kym, Yanbin Lao, Xiaochun Lou, Sean E. Mackey, Mark A. Matulenko, Peter T. Mayer, Christopher P. Miller, James Stambuli, Valentino J. Stella, Eric A. Voight, Zhi Wang, Geoff Zhang
  • Publication number: 20200266284
    Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 20, 2020
    Applicant: Tessera, Inc.
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10741452
    Abstract: Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric R. Miller, Stuart A. Sieg, Yann Mignot, Indira Seshadri, Christopher J. Waskiewicz
  • Publication number: 20200235094
    Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 23, 2020
    Applicant: TESSERA, INC.
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Publication number: 20200204701
    Abstract: A printed document client receives a first print stream for a soft copy document, determines whether one or more conditions for adding a graphical symbol to the printed document are satisfied, and when the one or more conditions for adding the graphical symbol to the printed document are satisfied, adds the graphical symbol to the first print stream to generate a second print stream that includes the graphical symbol, and outputs the second print stream to a printer so the graphical symbol is printed on the printed document corresponding to the soft copy document. The printed document can be a hard copy document or a soft copy document generated from the second print stream.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Inventors: Steven W. Irons, David R. Guilbault, Eric R. Lynn, Dale Shoup, Anthony Argenziano, Simon Okunev, Ian M. Miller
  • Patent number: 10692776
    Abstract: A semiconductor device includes etching fins into a bulk substrate in an active region, the bulk substrate including an intermediate layer formed over a base layer and a first semiconductor layer formed over the intermediate layer such that the fins extend through the first semiconductor layer into the intermediate layer to form tapered bottom portions of the fins within the intermediate layer and vertical fin sidewalls of a semiconductor portions of the fins within the first semiconductor layer. A second semiconductor layer is formed around the tapered bottom portions below the semiconductor portions of the fins such that the second semiconductor layer covers the tapered bottom portions to form a top surface proximal to the semiconductor portions of the fins that is substantially parallel to a bottom surface of the top surface of the base layer. A gate structure is formed around the fins.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric R. Miller, Marc Bergendahl, Kangguo Cheng, Yann Mignot
  • Publication number: 20200195574
    Abstract: Method and apparatus for facilitating accessing home surveillance device data, preferably an IP camera video stream, by a remote user device at the remote user device's instigation, over the Internet through a home router, the facilitating including incorporating a smart gateway in local communication with the home router and in persistent or intermittent communication with a remote Internet server to facilitate communication of data over the Internet at the remote user device's request through direct communication between the remote user device and the smart gateway, the smart gateway in local communication with the home surveillance device such as an IP camera, the direct communication facilitated by a “hole punch” type of technique.
    Type: Application
    Filed: July 18, 2019
    Publication date: June 18, 2020
    Inventors: Byron L. Hoffman, Eric R. Lachney, Michael R. Miller, Russell S. Vail
  • Patent number: 10668201
    Abstract: A dialysis system includes a filtration system capable of filtering a water stream, a water purification system capable of purifying said water stream in a non-batch process, a mixing system capable of producing a stream of dialysate from mixing one or more dialysate components with the water stream in a non-batch process, and a dialyzer system. The dialyzer may be a microfluidic dialyzer capable of being fluidly coupled to the stream of dialysate and a blood stream.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: June 2, 2020
    Assignees: Oregon State University, Outset Medical, Inc.
    Inventors: Julie S. Wrazel, James R. Curtis, Ladislaus Nonn, Richard B. Peterson, Hailei Wang, Robbie Ingram-Goble, Luke W. Fisher, Anna E. Garrison, M. Kevin Drost, Goran Jovanovic, Richard Todd Miller, Bruce W. Johnson, Alana Anderson, Eric K. Anderson
  • Publication number: 20200144131
    Abstract: A semiconductor device includes etching fins into a bulk substrate in an active region, the bulk substrate including an intermediate layer formed over a base layer and a first semiconductor layer formed over the intermediate layer such that the fins extend through the first semiconductor layer into the intermediate layer to form tapered bottom portions of the fins within the intermediate layer and vertical fin sidewalls of a semiconductor portions of the fins within the first semiconductor layer. A second semiconductor layer is formed around the tapered bottom portions below the semiconductor portions of the fins such that the second semiconductor layer covers the tapered bottom portions to form a top surface proximal to the semiconductor portions of the fins that is substantially parallel to a bottom surface of the top surface of the base layer. A gate structure is formed around the fins.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 7, 2020
    Inventors: Eric R. Miller, Marc Bergendahl, Kangguo Cheng, Yann Mignot
  • Patent number: 10640595
    Abstract: Acrylic copolymers that include the controlled placement of particular functional groups within the polymer structure are provided. The copolymers comprise a first reactive segment of including a functional group selected from the group consisting of a UV active functional group, a reactive functional group, a non-reactive functional group, and combinations thereof and a second segment including a functional group selected from the group consisting of a reactive functional group, a non-reactive functional group, and combinations thereof. The acrylic copolymers are manufactured via a controlled radical polymerization process. The copolymers are useful in the manufacture of adhesives and elastomers.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: May 5, 2020
    Assignee: Avery Dennison Corporation
    Inventors: Eric L. Bartholomew, William L. Bottorf, Kyle R. Heimbach, Brandon S. Miller, Michael T. Waterman, Michael Zajaczkowski