Abstract: A micro-valve includes an orifice plate including an orifice. The micro-valve further includes an actuating beam having a first end and a second end. The actuating beam also includes a base layer and a layer of piezoelectric material disposed on the base layer, a bottom electrode layer, and a top electrode layer. At an electrical connection portion of the actuating beam, the layer of piezoelectric material includes a first via, and a portion of the top electrode layer disposed within the first via, and a portion of the bottom electrode disposed beneath the first via. The actuating beam includes a base portion extending from the electrical connection portion and a cantilevered portion extending from the base portion. The cantilevered portion is movable in response to application of a differential electrical signal between the bottom electrode layer and the top electrode layer to one of open or close the micro-valve.

Abstract: A method for fabricating a wafer stack. The method includes forming a tantalum-nitride film on a substrate of the wafer stack using physical vapor deposition, forming a tantalum layer on the tantalum-nitride film using physical vapor deposition, and depositing indium on the tantalum layer using electroplating.

Abstract: A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

Abstract: A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.

Abstract: A marking system includes a valve body including an orifice plate including multiple orifices and multiple micro-valves. Each micro-valve includes an actuating beam movable from a closed position in which a corresponding one of the orifices is sealed by a portion of the actuating beam such that the micro-valve is closed, into a peak position in response to application of a control signal. A controller is configured to generate a control signal for each of the actuating beams, each control signal including a drive pulse having a predetermined voltage such that the actuating beam moves from the closed position into the peak position in which the corresponding orifice is open and returns to the closed position in a characteristic period, wherein the drive pulse has a duration that substantially corresponds to the characteristic period such that the actuating beam is in the closed position after the drive pulse is complete.

Abstract: A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.

Abstract: Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

Abstract: A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.

Abstract: A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.

Abstract: A micro-valve includes an orifice plate including an orifice. The micro-valve further includes an actuating beam having a first end and a second end. The actuating beam also includes a base layer and a layer of piezoelectric material disposed on the base layer, a bottom electrode layer, and a top electrode layer. At an electrical connection portion of the actuating beam, the layer of piezoelectric material includes a first via, and a portion of the top electrode layer disposed within the first via, and a portion of the bottom electrode disposed beneath the first via. The actuating beam includes a base portion extending from the electrical connection portion and a cantilevered portion extending from the base portion. The cantilevered portion is movable in response to application of a differential electrical signal between the bottom electrode layer and the top electrode layer to one of open or close the micro-valve.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: A semiconductor device includes a fin structure having a circular cylindrical shape, and including a first recess formed on a first side of the fin structure and a second recess formed on a second side of the fin structure opposite the first side, an inner gate formed inside the fin structure, and an inner gate insulating layer formed between the inner gate and an inner surface of the fin structure.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: A marking system includes a valve body including an orifice plate including multiple orifices and multiple micro-valves. Each micro-valve includes an actuating beam movable from a closed position in which a corresponding one of the orifices is sealed by a portion of the actuating beam such that the micro-valve is closed, into a peak position in response to application of a control signal. A controller is configured to generate a control signal for each of the actuating beams, each control signal including a drive pulse having a predetermined voltage such that the actuating beam moves from the closed position into the peak position in which the corresponding orifice is open and returns to the closed position in a characteristic period, wherein the drive pulse has a duration that substantially corresponds to the characteristic period such that the actuating beam is in the closed position after the drive pulse is complete.

Abstract: Methods for forming semiconductor fins include forming a protective layer around a base of a hardmask fin on an underlying semiconductor layer. A portion of the hardmask fin is etched away with an etch that is selective to the protective layer. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.

Abstract: Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial fins in a substrate, wherein the partial fins include top portions of fins of the finFET device; forming a bi-layer spacer on the top portions of the fins; complete etching of the fins in the substrate to form bottom portions of the fins of the finFET device; depositing an insulator between the fins; recessing the insulator enough to expose a region of the fins not covered by the bi-layer spacer; removing the exposed region of the fins to create a gap between the top and bottom portions of the fins; filling the gap with additional insulator. A method for forming a finFET device is also provided where placement of the fin spacer occurs after (rather than before) insulator deposition. A finFET device is also provided.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).