Patents by Inventor Eric R. Miller

Eric R. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10397109
    Abstract: At an outbound end of a tunnel from a first data network, a packet is analyzed to determine whether the packet is to be directed to a local target in the first data network or to be sent over the tunnel to a remote target in a second data network. A target address of the packet is present in both the first data network and the second data network. When the packet is to be directed to the remote target in the second data network, an octet in the target address of the packet is changed from a first value to a second value, the changing forming a modified packet. When the second value is stored in the octet, the modified packet is caused to be sent to the tunnel for delivery to the second data network.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric M. Anderson, Susan A. Hearn, Linwood E. Loving, Martin G. Mclaughlin, Daniel R. Miller, John B. Simmons
  • Patent number: 10396181
    Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Publication number: 20190259833
    Abstract: A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Marc Adam BERGENDAHL, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
  • Publication number: 20190259832
    Abstract: A semiconductor device includes a fin structure having a circular cylindrical shape, and including a first recess formed on a first side of the fin structure and a second recess formed on a second side of the fin structure opposite the first side, an inner gate formed inside the fin structure, and an inner gate insulating layer formed between the inner gate and an inner surface of the fin structure.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Marc Adam BERGENDAHL, Gauri KARVE, Fee Li LIE, Eric R. MILLER, Robert Russell ROBISON, John Ryan SPORRE, Sean TEEHAN
  • Publication number: 20190252244
    Abstract: A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.
    Type: Application
    Filed: February 13, 2018
    Publication date: August 15, 2019
    Applicant: Raytheon Company
    Inventors: Sean P. Kilcoyne, Eric R. Miller, George Grama
  • Patent number: 10381437
    Abstract: A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc Adam Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
  • Patent number: 10358463
    Abstract: The present disclosure provides novel macrocyclic peptides which inhibit the PD-1/PD-L1 and PD-L1/CD80 protein/protein interaction, and thus are useful for the amelioration of various diseases, including cancer and infectious diseases.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 23, 2019
    Assignee: Bristol-Myers Squibb Company
    Inventors: Michael Matthew Miller, Martin Patrick Allen, Ling Li, Michael S. Bowsher, Eric P. Gillis, Eric Mull, Qian Zhao, Li-Qiang Sun, David R. Langley, Paul Michael Scola
  • Publication number: 20190221805
    Abstract: In accordance with at least selected embodiments, the present disclosure or invention is directed to improved battery separators, high conductance separators, improved lead-acid batteries, such as flooded lead-acid batteries, high conductance batteries, improved systems, and/or, improved vehicles including such batteries, and/or methods of manufacture or use of such separators or batteries, and/or combinations thereof. In accordance with at least certain embodiments, the present disclosure or invention is directed to improved lead acid batteries incorporating the improved separators and which exhibit increased conductance. Particular, non-limiting examples may include lead acid battery separators having structure or features designed to improve conductance, lower ER, lower water loss, and the like.
    Type: Application
    Filed: September 1, 2017
    Publication date: July 18, 2019
    Inventors: Eric H. MILLER, Nicholas R. Shelton, William L. Walter
  • Patent number: 10355109
    Abstract: A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thamarai Selvi Devarajan, Sanjay C. Mehta, Eric R. Miller, Soon-Cheon Seo
  • Patent number: 10331708
    Abstract: A system for dynamic content delivery is provided. The system includes a control component to determine location, preferences, and state of a user. A delivery component dynamically selects and provides content to the user as a function of the user's location, preferences, and state.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 25, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Kevin T. Shields, William T. Flora, Bret P. O'Rourke, John Mark Miller, Eric P. Wilfrid, Nigel S. Keam, Steven N. Bathiche, Oliver R. Roup, Zachary L. Russell, Jon Marcus Randall Whitten
  • Publication number: 20190181461
    Abstract: The present disclosure relates membrane-electrode assemblies and electrochemical cells and liquid flow batteries produced therefrom. The membrane-electrode assemblies include a first porous electrode; an ion permeable membrane, having a first major surface and an opposed second major surface; a first discontinuous transport protection layer disposed between the first porous electrode and the first major surface of the ion permeable membrane; and a first adhesive layer in contact with the first porous electrode and at least one of the first discontinuous transport protection layer and the ion permeable membrane. The first adhesive layer is disposed along the perimeter of the membrane-electrode assembly.
    Type: Application
    Filed: August 9, 2017
    Publication date: June 13, 2019
    Inventors: Brian T. Weber, Brandon A. Bartling, Onur Sinan Yordem, Andrew T. Haug, John E. Abulu, Gregory M. Haugen, Kazuki Noda, Shunsuke Suzuki, Bharat R. Acharya, Daniel M. Pierpont, David J. Miller, Eric J. Iverson
  • Publication number: 20190172940
    Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).
    Type: Application
    Filed: February 5, 2019
    Publication date: June 6, 2019
    Inventors: Andrew M. Greene, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Eric R. Miller, Pietro Montanini
  • Patent number: 10304689
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrel structures. A plurality of first spacers is formed on sidewalls of the mandrel structures. A plurality of second spacers is formed on sidewalls of the first spacers. The plurality of first spacers is removed selective to the plurality of second spacers and mandrel structures. A cut mask is formed over a first set of second spacers of the plurality of second spacers and a first set of mandrel structures of the plurality of mandrel structures. A second set of second spacers of the plurality of spacers and a second set of mandrel structures of the plurality of mandrel structures remain exposed. One of the second set of mandrel structures and the second set of second spacers is removed selective to the second set of second spacers and the second set of mandrel structures, respectively.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gauri Karve, Fee Li Lie, Eric R. Miller, Stuart A. Sieg, John R. Sporre, Sean Teehan
  • Patent number: 10269931
    Abstract: Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10256326
    Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 10256239
    Abstract: A method of forming a semiconductor structure includes depositing a spacer material over a top surface of a substrate and two or more spaced-apart gates formed on the top surface of the substrate. The method also includes depositing a sacrificial liner over the spacer material and etching the sacrificial liner and the spacer material to expose portions of the top surface of the substrate between the two or more spaced-apart gates. The method further includes removing the sacrificial liner such that remaining spacer material forms two or more spacers between the two or more spaced-apart gates, each of the spacers including a first portion proximate the top surface of the substrate having a first width and a second portion above the first portion with a second width smaller than the first width.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian Pranatharthiharan, Eric R. Miller, Soon-Cheon Seo, John R. Sporre
  • Patent number: 10249738
    Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10249762
    Abstract: A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10243079
    Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andrew M. Greene, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Eric R. Miller, Pietro Montanini
  • Patent number: 10199503
    Abstract: Transistors and methods of forming the same include forming a semiconductor fin from a first material on dielectric layer. Material is etched away from the dielectric layer directly underneath a channel region of the semiconductor fin, with the semiconductor fin still being supported by the dielectric layer in a source and drain region. A gate stack is formed around the channel region of the semiconductor fin, with a portion of the gate stack underneath the semiconductor fin being larger than a portion of the gate stack above the semiconductor fin.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: February 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan