Patents by Inventor Eric R. Miller

Eric R. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9905643
    Abstract: A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 9893166
    Abstract: Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: February 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Publication number: 20170373167
    Abstract: Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.
    Type: Application
    Filed: June 14, 2017
    Publication date: December 28, 2017
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Publication number: 20170373166
    Abstract: Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Publication number: 20170352657
    Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.
    Type: Application
    Filed: December 7, 2016
    Publication date: December 7, 2017
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Publication number: 20170323951
    Abstract: Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.
    Type: Application
    Filed: June 6, 2017
    Publication date: November 9, 2017
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 9786666
    Abstract: A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a silicon germanium alloy is formed in a pFET device region. A thermal anneal is then used to convert the fin stack into a silicon germanium alloy fin precursor. A thermal oxidation process follows that converts the silicon fin precursor into a silicon fin and the silicon germanium alloy fin precursor into a silicon germanium alloy fin. Functional gate structures can be formed straddling over each of the various fins.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 9754942
    Abstract: A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Jessica Dechene, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 9748146
    Abstract: A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: August 29, 2017
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Jessica Dechene, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Publication number: 20170229463
    Abstract: A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.
    Type: Application
    Filed: June 1, 2016
    Publication date: August 10, 2017
    Inventors: MARC A. BERGENDAHL, KANGGUO CHENG, JESSICA DECHENE, FEE LI LIE, ERIC R. MILLER, JEFFREY C. SHEARER, JOHN R. SPORRE, SEAN TEEHAN
  • Publication number: 20170229350
    Abstract: A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.
    Type: Application
    Filed: August 18, 2016
    Publication date: August 10, 2017
    Inventors: MARC A. BERGENDAHL, KANGGUO CHENG, JESSICA DECHENE, FEE LI LIE, ERIC R. MILLER, JEFFREY C. SHEARER, JOHN R. SPORRE, SEAN TEEHAN
  • Patent number: 9728622
    Abstract: Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Publication number: 20170221773
    Abstract: A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Inventors: Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Publication number: 20170221708
    Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 3, 2017
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Publication number: 20170222024
    Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
    Type: Application
    Filed: December 2, 2016
    Publication date: August 3, 2017
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 9716184
    Abstract: In an embodiment, this disclosure relates to a method of creating an alignment feature within a sidewall image transfer process by the addition of a block mask. The presence of the alignment feature would enable better overlay and alignment for subsequent lithographic stacks.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Sivananda K. Kanakasabapathy, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Publication number: 20170179305
    Abstract: In an embodiment, this disclosure relates to a method of creating an alignment feature within a sidewall image transfer process by the addition of a block mask. The presence of the alignment feature would enable better overlay and alignment for subsequent lithographic stacks.
    Type: Application
    Filed: May 18, 2016
    Publication date: June 22, 2017
    Inventors: Kangguo Cheng, Sivananda K. Kanakasabapathy, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Publication number: 20170170301
    Abstract: A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.
    Type: Application
    Filed: August 5, 2016
    Publication date: June 15, 2017
    Inventors: Thamarai Selvi Devarajan, Sanjay C. Mehta, Eric R. Miller, Soon-Cheon Seo
  • Patent number: 9627277
    Abstract: A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 9620590
    Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan