Abstract: A memory circuit having: a memory array including one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.

Abstract: Disclosed is a system for a facility supporting an access controller, at least one ingress card reader and an auto-enrollment type controller including a front panel having a single button, a controller board, a terminal block for connecting at least the one ingress card reader to the auto-enrollment type controller board and to connect the auto-enrollment type controller to door locks, and a mounting plate, with the auto-enrollment type controller being configured by a user according to operational requirements of the facility by the user asserting the button for a defined period of time.

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

Abstract: An imaging cell includes a skimming gate transistor coupled between a photosensitive charge node and an intermediate node and a transfer gate transistor coupled between the intermediate node and a sense node. The skimming gate transistor includes a vertical gate electrode structure formed by a first capacitive deep trench isolation extending into a substrate and a second capacitive deep trench isolation extending into the substrate. A channel of the skimming gate transistor is positioned between the first and second capacitive deep trench isolations. Each capacitive deep trench isolation is formed by a trench that is lined with an insulating liner and filled with a conductive or semiconductive material.

Abstract: Each pixel of a global shutter back-side illuminated image sensor includes a photosensitive area. On a front surface, a first transistor includes a vertical ring-shaped electrode penetrating into the photosensitive area and laterally delimiting a memory area. The memory area penetrates into the photosensitive area less deeply than the insulated vertical ring-shaped electrode. A read area is formed in an intermediate area which is formed in the memory area. The memory area, the intermediate area and read area define a second transistor having an insulated horizontal electrode forming a gate of the second transistor. The memory area may be formed by a first and second memory areas and an output signal is generated indicative of a difference between charge stored in the first memory area and charge stored in the second memory area after a charge transfer to the first memory area.

Abstract: A sensor array includes pixel kernels, wherein each pixel kernel includes RGB pixels, the RGB pixels being configured to provide a plurality of color signals, and Z pixels each having a single memory element, the Z pixels being configured to provide a single TOF signal. Each pixel kernel includes two to four Z pixels. The RGB and Z pixels can be integrated together on a single sensor array.

Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.

Abstract: A semiconductor device includes a first semiconductor substrate with a first transistor therein. The first transistor includes a first source-drain formed by a doped region in the first semiconductor substrate. An intermediary insulating layer is formed on and above the first semiconductor substrate. A second semiconductor substrate is formed on and above the intermediary insulating layer. A second transistor is formed in the second semiconductor substrate, and includes a second source-drain formed by a doped region in the second semiconductor substrate. A trench is formed in the second semiconductor substrate and in contact with the doped region for the second semiconductor substrate. The trench has a thickness equal to that of the second semiconductor substrate. Metal wiring extends from a contact with the doped region for the first source-drain, through the intermediary insulating layer and the trench, to make electrical contact with the doped region for the second source-drain.

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

Abstract: A photosensor is formed within a semiconductor substrate layer having a front side and a back side. An isolation structure delimits an active region of the semiconductor substrate layer which includes a charge collecting region. The front side of semiconductor substrate layer includes a charge transfer circuit. A reflecting mirror is mounted at the back side of the semiconductor substrate layer. The reflecting mirror includes a pupil opening configured to admit light into the active region at the back side. An underside reflective surface of the reflecting mirror is configured to reflect light received from the active region back into the active region.

Abstract: An electronic image capture device includes a first portion and a second portion. The first portion is formed by a substrate wafer provided on one side with electronic circuits and a dielectric layer with a network of electrical connections and external electrical contacts on an outer surface. The second portion includes a pixel wafer capable of generating electrical signals under the effect of light, a substrate wafer mounted to the pixel wafer and provided with electronic circuits and a dielectric layer with a network of electrical connections and external electrical contacts on an outer surface. The outer surfaces and external electrical contacts are bonded to each other so as to mount the first portion to the second portion. A connection pad extends through a hole in the pixel wafer to make electrical connection to the network of electrical connections of the second portion.

Abstract: An image sensor arranged inside and on top of a semi-conductor substrate having a front surface and a rear surface, the sensor including a plurality of pixels, each including: a photosensitive area, a reading area, and a storage area extending between the photosensitive area and the reading area; a vertical insulated electrode including an opening of transfer between the photosensitive area and the storage area; and at least one insulation element among the following: a) a layer of an insulating material extending under the surface of the photosensitive area and of the storage area and having its front surface in contact with the rear surface of the electrode; and b) an insulating wall extending vertically in the opening, or under the opening.

Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.

Abstract: An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors.

Abstract: A back-side illuminated pixel including a semiconductor substrate of a first conductivity type coated, on the front side of the pixel, with a three-layer assembly successively including a first layer of the second conductivity type, an insulating layer, and a second semiconductor layer. The three-layer assembly is interrupted in a central portion of the pixel by a transfer region of the first conductivity type laterally delimited by an insulated conductive wall extending from the front surface, Transistors are formed in the second semiconductor layer.

Abstract: An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors.

Abstract: A lighting system and method for generating an output light beam representative of a target natural light are provided. The lighting system includes a plurality of solid-state light emitters each emitting a light sub-beam having an individual spectrum. The individual spectra of the solid-state light emitters collectively cover a visible portion of the natural light spectral profile and exclude infrared and ultraviolet components. The lighting system further includes a combining assembly combining the light sub-beams into the output light beam. A control module controls an intensity of the light sub-beam from each of the solid-state light emitters such that the resulting combined spectral profile of the output light beam is representative of a natural light spectral profile of the target natural light over its visible portion.

Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.

Abstract: A time-of-flight detection pixel includes a photosensitive area and at least two assemblies. Each assembly includes: a charge storage area; a transfer transistor configured to control charge transfer from the photosensitive area to the charge storage area; and readout circuit configured to non-destructively measure a quantity of charges stored in the charge storage area.

Abstract: An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors.