Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a first reference clock signal and generate a first reference time signal based on the timing signal and the first reference clock signal. The IC chip is configured to generate a second reference time signal based on the first reference time signal and a second reference clock signal, different from the first reference clock signal The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The IC chip is configured to synchronize one or more actions performed by the IC chip based on one or more of the first reference time signal or the second reference time signal.

Abstract: In an embodiment, an apparatus includes a first baseband section to receive a calibration signal; a first radio frequency (RF) section configured to generate a RF calibration signal based on modulating the calibration signal. The calibration signal comprises an orthogonal code based signal. The apparatus includes a second RF section to receive the RF calibration signal and generate a received calibration signal based on demodulating the RF calibration signal; a calibration section; a first antenna electrically coupled to the first RF section and configured to transmit the RF calibration signal; and a second antenna electrically coupled to the second RF section and configured to receive the RF calibration signal. The calibration section is configured to determine one or more of gain, baseband delay, or RF delay to calibrate the first RF section; and the second antenna is switchable between receiving the RF calibration signal and transmitting an encoded data signal.

Abstract: In an embodiment, an apparatus includes one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal. The apparatus includes phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal.

Abstract: In an embodiment, a communications system includes a first transmitter electrically coupled to a first antenna of a phased array antenna, the first transmitter configured to receive an input signal, apply a first baseband frequency shift to the input signal to generate a first baseband frequency shifted input signal, generate a first modulated signal based on the first baseband frequency shifted input signal and transmit the first modulated signal by the first antenna. The communications system includes a second transmitter electrically coupled to a second antenna of the phased array antenna. The second transmitter configured to receive the input signal, apply a second baseband frequency shift, different from the first baseband frequency shift, to the input signal to generate a second baseband frequency shifted input signal, generate a second modulated signal based on the second baseband frequency shifted input signal, and transmit the second modulated signal by the second antenna.

Abstract: In an embodiment, an apparatus includes a transmit section including a first baseband section and a first radio frequency (RF) section, wherein the transmit section is configured to receive a calibration signal, the first RF section is configured to generate a RF calibration signal based on modulating the calibration signal. The calibration signal comprises an orthogonal code based signal; and a receive section configured to receive the RF calibration signal over-the-air, the receive section includes a second RF section and a calibration section, the second RF section is configured to generate a received calibration signal based on the RF calibration signal, the received calibration signal and a reference signal associated with the RF calibration signal comprise inputs to the calibration section and the calibration section is configured to determine one or more of gain, baseband delay, or RF delay compensation values, based on the inputs, to calibrate the transmit section.

Abstract: In an embodiment, a communications system includes a first transmitter including a digital beamforming baseband section configured to receive an input signal to be transmitted, the input signal at a baseband frequency, and a modulation section electrically coupled to the digital beamforming baseband section and a first antenna of a phased array antenna. The modulation section is configured to receive a local oscillator signal at a first local oscillator frequency and apply a baseband frequency shift to the input signal to generate a baseband frequency shifted input signal. The modulation section generates a modulated signal based on the input signal. The communication system includes a second transmitter included in a second IC chip of the plurality of IC chips electrically coupled to a second antenna and configured to provide a second modulated signal at the carrier frequency and a second LO leakage signal at a second local oscillator frequency.

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal. The IC chips is configured to a reference time signal based on the timing signal and the reference clock signal. The IC chip includes a phase lock loop (PLL). The PLL is synchronized based on the reference time signal.

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal and generate a first reference time signal based on the timing signal and the reference clock signal. The IC chip includes a clock phase lock loop (PLL) configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal; the IC chip is further configured to generate a second reference time signal based on the first reference time signal and the second reference clock signal. The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The second reference time signal has a finer count resolution than the first reference time signal for a same time period.

Abstract: In an embodiment, a communications system includes a first transmitter including a digital beamforming baseband section configured to receive an input signal to be transmitted, the input signal at a baseband frequency, and a modulation section electrically coupled to the digital beamforming baseband section and a first antenna of a phased array antenna. The modulation section is configured to receive a local oscillator signal at a first local oscillator frequency and apply a baseband frequency shift to the input signal to generate a baseband frequency shifted input signal. The modulation section generates a modulated signal based on the input signal. The communication system includes a second transmitter included in a second IC chip of the plurality of IC chips electrically coupled to a second antenna and configured to provide a second modulated signal at the carrier frequency and a second LO leakage signal at a second local oscillator frequency.

Abstract: In an embodiment, an apparatus includes a transmit section including a first baseband section and a first radio frequency (RF) section, wherein the transmit section is configured to receive a calibration signal, the first RF section is configured to generate a RF calibration signal based on modulating the calibration signal. The calibration signal comprises an orthogonal code based signal; and a receive section configured to receive the RF calibration signal over-the-air, the receive section includes a second RF section and a calibration section, the second RF section is configured to generate a received calibration signal based on the RF calibration signal, the received calibration signal and a reference signal associated with the RF calibration signal comprise inputs to the calibration section and the calibration section is configured to determine one or more of gain, baseband delay, or RF delay compensation values, based on the inputs, to calibrate the transmit section.

Abstract: In an embodiment, a communications system includes a transmitter including a digital beamforming baseband section including a digital mixer, the digital beamforming section configured to receive an input signal to be transmitted, the input signal at a baseband frequency; and a modulation section electrically coupled to the digital beamforming baseband section, the modulation section including an up converter configured to receive a local oscillator signal at a local oscillator frequency. The digital mixer is configured to apply a baseband frequency shift to the input signal to generate a baseband frequency shifted input signal at a different frequency from the baseband frequency. The up converter is configured to up convert the baseband frequency shifted input signal based on the local oscillator signal to generate a modulated signal at a carrier frequency, wherein the local oscillator frequency is different from the carrier frequency.

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal. The IC chips is configured to a reference time signal based on the timing signal and the reference clock signal. The IC chip includes a phase lock loop (PLL). The PLL is synchronized based on the reference time signal.

Abstract: In an embodiment, an apparatus included in a communications system includes a transmit section including a first baseband section and a first radio frequency (RF) section, wherein the transmit section is configured to receive a calibration signal, the first RF section is configured to generate a RF calibration signal based on the calibration signal, and wherein the calibration signal comprises an orthogonal code based signal; and a receive section configured to receive the RF calibration signal over-the-air, wherein the receive section includes a second RF section and a calibration section, wherein the second RF section is configured to generate a received calibration signal based on the RF calibration signal, and wherein the calibration section is configured to determine one or more of gain, baseband delay, or RF delay compensation values, based on the inputs, to calibrate the transmit section.

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal and generate a first reference time signal based on the timing signal and the reference clock signal. The IC chip includes a clock phase lock loop (PLL) configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal; the IC chip is further configured to generate a second reference time signal based on the first reference time signal and the second reference clock signal. The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The second reference time signal has a finer count resolution than the first reference time signal for a same time period.

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. Each of the first, second, and third reference time signals is associated with a count of a number of cycles of the reference clock signal starting from a same particular cycle of the reference clock signal.

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips include respectively first, second, and third phase lock loop (PLL). The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. The first, second, and third PLLs are synchronized to each other based on the respective first, second, and third reference time signals.

Abstract: In an embodiment, an apparatus included in a communications system includes a transmit section including a first baseband section and a first radio frequency (RF) section, wherein the transmit section is configured to receive a calibration signal, the first RF section is configured to generate a RF calibration signal based on the calibration signal, and wherein the calibration signal comprises an orthogonal code based signal; and a receive section configured to receive the RF calibration signal over-the-air, wherein the receive section includes a second RF section and a calibration section, wherein the second RF section is configured to generate a received calibration signal based on the RF calibration signal, and wherein the calibration section is configured to determine one or more of gain, baseband delay, or RF delay compensation values, based on the inputs, to calibrate the transmit section.

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. Each of the first, second, and third reference time signals is associated with a count of a number of cycles of the reference clock signal starting from a same particular cycle of the reference clock signal.