Abstract: A memory circuit with an error correcting system comprising an address bus (102), an input data bus (108), and an output data bus (115), the circuit comprising a memory having an address bus (113), a data bus (114) and an error correcting circuit comprising an encoder (107). A first address register (104) is connected to the input address bus of the circuit for successively storing addresses corresponding to memory write operations only. A second data register (105) is connected to the input data bus of the circuit (108) for storing data transmitted to the encoder (107). Circuits make it possible to introduce a one-cycle shift into the memory writes, without modifying reads, giving the encoder more time to compute error correcting codes.

Abstract: A component of an integrated circuit comprises a first capacitor and a second capacitor series-connected between a first node and a second node of the component. This has application to logic circuits and bistable circuits, for example, SRAM type memories, flip-flop trigger circuits, etc.

Abstract: A method is for controlling reading of a dynamic random access memory (DRAM) including memory cells connected to a bit line of a memory plane of the DRAM and associated with a main reference cell connected to a reference bit line. The method may include reading and refreshing the contents of the memory cell and pre-charging the bit line, the reference bit line and the main reference cell for a subsequent read access. During reading and refreshing the memory cell, the main reference cell and a secondary reference cell connected to the bit line may be activated and, after having deactivated the two reference cells, they are pre-charged to a final pre-charge voltage. The final pre-charge voltage may be chosen to be less than or greater than (as a function of the NMOS or PMOS technology used, respectively) half the sum of a high-state storage voltage and a low-state storage voltage.

Abstract: A device for reading from a capacitive memory cell, including a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance; a refreshment means distinct from the comparator, the refreshment means having a low output impedance and being controlled by the comparator to impose a refreshment voltage to the memory cell; and means for controllably connecting the refreshment means to the memory cell.

Abstract: A device for reading from a capacitive memory cell, including a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance; a refreshment means distinct from the comparator, the refreshment means having a low output impedance and being controlled by the comparator to impose a refreshment voltage to the memory cell; and means for controllably connecting the refreshment means to the memory cell.

Abstract: A method is for controlling reading of a dynamic random access memory (DRAM) including memory cells connected to a bit line of a memory plane of the DRAM and associated with a main reference cell connected to a reference bit line. The method may include reading and refreshing the contents of the memory cell and pre-charging the bit line, the reference bit line and the main reference cell for a subsequent read access. During reading and refreshing the memory cell, the main reference cell and a secondary reference cell connected to the bit line may be activated and, after having deactivated the two reference cells, they are pre-charged to a final pre-charge voltage. The final pre-charge voltage may be chosen to be less than or greater than (as a function of the NMOS or PMOS technology used, respectively) half the sum of a high-state storage voltage and a low-state storage voltage.

Abstract: At a charging phase, a capacitor (PC) is charged through two complementary charging transistors (TR1, TR2) connected in series to a first terminal (T1) of the capacitor (PC). At a voltage multiplication phase, an input voltage (Vdd) is delivered to the second terminal (T2) of the capacitor and an output voltage (Vout), increased with respect to the input voltage, is recovered at the first terminal (T1) of the, capacitor, and the capacitor is discharged during a discharging phase. During three phases, the substrate (BK2) of the charging transistor (TR2) directly connected to the first terminal (T1) of the capacitor is slaved to the source (S2) of this same charging transistor (TR2), while still keeping the source-substrate junction and the drain-substrate junction of this charging transistor (TR2) reverse-biased.