Abstract: A less lethal weapon projectile having an overall cylindrical shape and including a front end (4) shaped as an at least approximately spherical cap and a rear end (2) includes: a core (6) made from aluminium foam, having an overall cylindrical shape and including a front end (16) and a rear end (13) with a rear face (14), the front end (16) shaped as an at least substantially spherical cap; a base (5) assembled with the rear end (13) of the core (6) and including a front wall (9), arranged transversely and covering the rear face (14) of the core (6); and an outer case (7) covering at least the front end (16) of the core (6). The center of gravity and the center of thrust correspond perfectly, so that the projectile has good external ballistics.

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract: The present invention relates to a Network on chip comprising a torus matrix of processing elements formed by a juxtaposition of bricks in rows and columns, each brick comprising a longitudinal extra-connection bus segment connecting two terminals situated on opposite transverse edges of the brick on a first axis; two longitudinal intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite transverse edges on a second axis symmetrical to the first axis with respect to the center of the brick; a transverse extra-connection bus segment connecting two terminals situated on opposite longitudinal edges of the brick on a third axis; and two transverse intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite longitudinal edges on a fourth axis symmetrical to the third axis with respect to the center of the brick.

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract: An interconnection network with m first electronic circuits and n second electronic circuits, comprising m interconnection sub-networks, each interconnection sub-network including: at least one addressing bus and one information transfer bus connecting one of the m first circuits to all the n second circuits, the information transfer bus comprising a plurality of portions of signal transmission lines connected to each other through signal repeater devices, and a controller device that controls the signal repeater devices, at least one of the signal repeater devices is controlled to be active depending on a value of an addressing signal to be sent to the addressing bus by said one of the m first circuits to the controller device, where m and n are integer numbers greater than 1.

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract: The present invention relates to a Network on chip comprising a torus matrix of processing elements formed by a juxtaposition of bricks in rows and columns, each brick comprising a longitudinal extra-connection bus segment connecting two terminals situated on opposite transverse edges of the brick on a first axis; two longitudinal intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite transverse edges on a second axis symmetrical to the first axis with respect to the center of the brick; a transverse extra-connection bus segment connecting two terminals situated on opposite longitudinal edges of the brick on a third axis; and two transverse intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite longitudinal edges on a fourth axis symmetrical to the third axis with respect to the center of the brick.

Abstract: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

Abstract: An interconnection network with m first electronic circuits and n second electronic circuits, comprising m interconnection sub-networks, each comprising: one addressing bus and one information transfer bus connecting one of the m first circuits to all the n second circuits and comprising a plurality of electrically conducting wire segments connected to each other through signal repeater devices, means of controlling the repeater devices, capable of making at least one of the repeater devices active depending on the value of an addressing signal, the active repeater device forming a communication path in the information transfer bus for data signals between said one of the m first circuits and one of the n second circuits or between several of the n second circuits, where m and n are integer numbers greater than 1.

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract: A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage (VDDMMOCK) for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract: An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal: an image of the input signals if said input signals are identical, or inactive, if the input signals are different from each other.

Abstract: A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

Abstract: An embodiment of the invention relate to a memory device including a memory plane composed of memory cells located at the intersection of lines and columns, and a dummy path designed to output a signal to activate read amplifiers arranged at the bottom of the columns in the memory plane, said dummy path including dummy memory cells connected between two dummy bit lines means of selecting at least one dummy cell designed to discharge at least one of the dummy bit lines, and control means connected to the two dummy bit lines to generate said activation signal, characterized in that said device includes means of programming the number of selected cells to discharge at least said dummy bit line, to adjust the time at which said activation signal is output.

Abstract: A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages.

Abstract: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

Abstract: A RAM memory integrated circuit, in particular a SRAM memory integrated circuit, includes a matrix of memory cells that are arranged between two bit lines via two access transistors. The bit lines are intended in one case to be discharged and in the other case to be maintained at a high precharge potential during a read operation. The bit line of each column of the matrix that is intended to be maintained at the high precharge potential is produced in the form of at least two partial bit lines. The memory cells of each column are implanted in the form of groups of cells which are alternately connected to one or the other of the partial bit lines, respectively.

Abstract: A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first and second storage circuits each have a respective input and output. An isolation circuit provides electrical isolation of the input of the first storage device from the output of the second storage device, except during access to the first and second storage circuits.