Patents by Inventor Frankie F. Roohparvar

Frankie F. Roohparvar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONTENT ADDRESSABLE MEMORY
    Publication number: 20120218822
    Abstract: NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In addition, the NAND architecture non-volatile CAM memory operates with reduced power consumption characteristics for low power and portable applications. In one NAND architecture non-volatile CAM memory embodiment a wired NOR match line array is utilized. In another embodiment a NAND match line array is shown. In yet other embodiments, hierarchal addressing, hash addressing, tree search and algorithmic/hardware engine based search is detailed utilizing both conventional NAND architecture non-volatile Flash memory arrays and dedicated NAND architecture CAM arrays utilizing wired NOR and wired NAND match lines.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 30, 2012
    Inventor: Frankie F. Roohparvar
  • Methods of operating memories including characterizing memory cell signal lines
    Patent number: 8254180
    Abstract: Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Methods include selecting a memory cell signal line of a memory and characterizing the memory cell signal line by determining an RC time constant of the memory cell signal line.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: August 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Jung-Sheng Hoei, Jonathan Pabustan, Vishal Sarin, William H. Radke, Frankie F. Roohparvar
  • Analog sensing of memory cells with a source follower driver in a semiconductor memory device
    Patent number: 8254182
    Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: August 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY
    Publication number: 20120206964
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate.
    Type: Application
    Filed: April 24, 2012
    Publication date: August 16, 2012
    Inventor: Frankie F. Roohparvar
  • CELL OPERATION MONITORING
    Publication number: 20120195126
    Abstract: Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Atypical cell, block, string, column, row, etc. . . . operation is monitored and locations and type of atypical operation stored. Adjustment of operation is performed based upon the atypical cell operation.
    Type: Application
    Filed: April 16, 2012
    Publication date: August 2, 2012
    Inventor: Frankie F. Roohparvar
  • Soft landing for desired program threshold voltage
    Patent number: 8223551
    Abstract: Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: July 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jung-Sheng Hoei, Jonathan Pabustan
  • Memory devices having strings of series-coupled memory cells selectively coupled to different bit lines
    Patent number: 8218348
    Abstract: Memory devices where ends of series-coupled strings of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device or by using one bit line as a ground node for sensing current flow through the strings. The use of bit lines for virtual grounding is further suitable to other array architectures.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: July 10, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Reduction of quick charge loss effect in a memory device
    Patent number: 8213233
    Abstract: Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: July 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, William Saiki, Frankie F. Roohparvar
  • PROCESSORS FOR PROGRAMMING MULTILEVEL-CELL NAND MEMORY DEVICES
    Publication number: 20120166720
    Abstract: In an embodiment, a processor includes a storage device. The processor is configured to request first data from a first location of a memory device. The storage device is configured to receive and to store the first data from the memory device. The processor is configured to attempt to write second data to the first location of the memory device. The processor is configured to write the first data stored in the storage device and the second data to one or more other locations of the memory device if the attempt to write second data to the first location of the memory device fails.
    Type: Application
    Filed: March 6, 2012
    Publication date: June 28, 2012
    Inventor: Frankie F. Roohparvar
  • Non-volatile memory device having assignable network identification
    Patent number: 8209477
    Abstract: Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: June 26, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Memory device reference cell programming method and apparatus
    Patent number: 8203886
    Abstract: Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: June 19, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar
  • Memory devices and their operation with different sets of logical erase blocks
    Patent number: 8199587
    Abstract: Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a first size the logical erase blocks of the second set of logical erase blocks each have a second size different than the first size.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: June 12, 2012
    Assignee: Round Rock Research, LLC
    Inventor: Frankie F. Roohparvar
  • PROGRAMMING MEMORY CELLS WITH ADDITIONAL DATA FOR INCREASED THRESHOLD VOLTAGE RESOLUTION
    Publication number: 20120144101
    Abstract: Methods for programming memory and memory devices are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example.
    Type: Application
    Filed: February 9, 2012
    Publication date: June 7, 2012
    Inventors: Vishal Sarin, Frankie F. Roohparvar
  • Read method for MLC
    Patent number: 8189382
    Abstract: Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Cell reads are performed multiple times and the read threshold voltages averaged to more closely approximate actual threshold voltage and to compensate for random noise.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: May 29, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Programming rate identification and control in a solid state memory
    Patent number: 8179725
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: May 15, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT
    Publication number: 20120117313
    Abstract: In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.
    Type: Application
    Filed: January 17, 2012
    Publication date: May 10, 2012
    Inventors: Vishal SARIN, Frankie F. Roohparvar, Jonathan Pabustan, Jung-Sheng Hoei
  • MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE
    Publication number: 20120113723
    Abstract: In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.
    Type: Application
    Filed: January 20, 2012
    Publication date: May 10, 2012
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • CONFIGURATION FINALIZATION ON FIRST VALID NAND COMMAND
    Publication number: 20120113727
    Abstract: A startup method and circuit to allow high current consumption for startup processes of a low operating voltage memory device such as a NAND device until the receipt of a valid command to the memory device. Upon receipt of a valid command, startup functions are ceased at the high current consumption, and normal operation begins without the need for using an unreliable low voltage power on reset circuit.
    Type: Application
    Filed: January 19, 2012
    Publication date: May 10, 2012
    Inventor: Frankie F. Roohparvar
  • Increased NAND flash memory read throughput
    Patent number: 8174892
    Abstract: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: May 8, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Dzung H. Nguyen, Frankie F. Roohparvar
  • Apparatus and method for increasing data line noise tolerance
    Patent number: 8174919
    Abstract: Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data line charge voltage with a current source.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: May 8, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Chia-Shing Jason Yu, Jung-Sheng Hoei, Vishal Sarin