Patents by Inventor Frankie F. Roohparvar

Frankie F. Roohparvar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Increased NAND flash memory read throughput
    Patent number: 8593870
    Abstract: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: November 26, 2013
    Assignee: Round Rock Research, LLC
    Inventors: Dzung H. Nguyen, Frankie F. Roohparvar
  • Programming error correction code into a solid state memory device with varying bits per cell
    Patent number: 8578244
    Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: November 5, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • METHODS OF READING MEMORY CELLS
    Publication number: 20130286739
    Abstract: Strings of series-coupled memory cells selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional memory array architectures. Reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device.
    Type: Application
    Filed: June 24, 2013
    Publication date: October 31, 2013
    Inventor: Frankie F. Roohparvar
  • Sensing memory cells
    Patent number: 8565024
    Abstract: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: October 22, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jung Sheng Hoei, Giulio-Giuseppe Marotta
  • Non-volatile memory device having assignable network identification
    Patent number: 8560766
    Abstract: Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: October 15, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • N WELL IMPLANTS TO SEPARATE BLOCKS IN A FLASH MEMORY DEVICE
    Publication number: 20130256831
    Abstract: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.
    Type: Application
    Filed: May 23, 2013
    Publication date: October 3, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Programming rate identification and control in a solid state memory
    Patent number: 8547748
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: October 1, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Macro and command execution from memory array
    Patent number: 8543874
    Abstract: Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device. Decode blocks adapted to interpret instructions and data stored in the memory device. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: September 24, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Benjamin Louie
  • Configurable digital and analog input/output interface in a memory device
    Patent number: 8526243
    Abstract: Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: September 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
  • Reducing noise in semiconductor devices
    Patent number: 8488385
    Abstract: The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: July 16, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jung Sheng Hoei
  • Memory arrays and memory devices
    Patent number: 8472254
    Abstract: Strings of series-coupled memory cells selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional memory array architectures. Reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: June 25, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Analog sensing of memory cells with a source follower driver in a semiconductor memory device
    Patent number: 8467250
    Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: June 18, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • N well implants to separate blocks in a flash memory device
    Patent number: 8455974
    Abstract: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: June 4, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • APPARATUS HAVING INDICATIONS OF MEMORY CELL DENSITY AND METHODS OF THEIR DETERMINATION AND USE
    Publication number: 20130135926
    Abstract: Methods and apparatus utilizing indications of memory cell density facilitate management of memory density of a memory device. By permitting each of a plurality of portions of a memory array of the memory device to be assigned a corresponding memory cell density determined through an evaluation of those portions of the memory array, better performing portions of the memory array may not be hindered by lesser performing portions of the memory array.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Inventors: Frankie F. ROOHPARVAR, Vishal Sarin
  • Apparatus having a string of memory cells
    Patent number: 8441858
    Abstract: Apparatus having a string of memory cells are useful in semiconductor memory. Some apparatus have circuitry configured to program memory cells of the string in a particular sequence. Some apparatus have circuitry configured to program a threshold voltage of a selected memory cell in the string to match a target voltage compensating, at least in part, for a voltage drop across any unselected memory cells in the string on a source side of the selected memory cell during a sensing operation. Some apparatus have circuitry configured to maintain a resistance presented by source-side unselected memory cells of the string the same between a program verify operation and a later read operation.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: May 14, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Analog sensing of memory cells with a source follower driver in a semiconductor memory device
    Patent number: 8422310
    Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: April 16, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Reading data from memory cells including storing charges to analog storage devices
    Patent number: 8411511
    Abstract: Methods of reading data from memory cells. Such methods include subjecting an analog storage device to a voltage level indicative of a threshold voltage of a memory cell to store a charge to the analog storage device, and generating an analog voltage from the stored charge.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: April 2, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Coarse and fine programming in a solid state memory
    Patent number: 8400826
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: March 19, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • Memory adapted to program a number of bits to a memory cell and read a different number of bits from the memory cell
    Patent number: 8385121
    Abstract: A memory has a memory array with a memory cell. The memory is adapted to program a first number of bits into the memory cell. The memory is adapted to sense a second number of bits, different from the first number of bits, from the memory cell.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: February 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Jonathan Pabustan, Frankie F. Roohparvar
  • Memory controller self-calibration for removing systemic influence
    Patent number: 8379446
    Abstract: Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: February 19, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei