Patents by Inventor Frankie F. Roohparvar

Frankie F. Roohparvar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Analog read and write paths in a solid state memory device
    Patent number: 8363473
    Abstract: A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: January 29, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin
  • Sensing of memory cells in NAND flash
    Patent number: 8355283
    Abstract: An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash memory array is read by applying an elevated voltage to the source line, an elevated pass voltage (Vpass) is placed on the gates of the unselected cells of the string to place them in a pass through mode of operation, and a read gate voltage (Vg) is applied to the gate of the selected cell. The selected memory cell operates as a source follower to set a voltage on the coupled bit line at the read gate voltage minus the threshold voltage of the cell (Vg?Vt), allowing the voltage of the cell to be directly sensed or sampled.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: January 15, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin
  • PROGRAMMING METHODS AND MEMORIES
    Publication number: 20130010542
    Abstract: Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.
    Type: Application
    Filed: July 6, 2011
    Publication date: January 10, 2013
    Inventors: Vishal Sarin, William H. Radke, Frankie F. Roohparvar
  • Programming a memory device to increase data reliability
    Patent number: 8345486
    Abstract: Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group of memory cells of the array having a relative reliability corresponding to the target reliability.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: January 1, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT
    Publication number: 20120331217
    Abstract: In one or more embodiments, a memory device has an adjustable programming window with a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.
    Type: Application
    Filed: September 7, 2012
    Publication date: December 27, 2012
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jonathan Pabustan, Jung-Sheng Hoei
  • COARSE AND FINE PROGRAMMING IN A SOLID STATE MEMORY
    Publication number: 20120314503
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.
    Type: Application
    Filed: August 21, 2012
    Publication date: December 13, 2012
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • METHOD FOR KINK COMPENSATION IN A MEMORY
    Publication number: 20120307564
    Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
    Type: Application
    Filed: August 14, 2012
    Publication date: December 6, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Violante Moschiano, Frankie F. Roohparvar, Giovanni Santin, Vishal Sarin, Allahyar Vahidimowlavi, Tommaso Vali
  • ANALOG SENSING OF MEMORY CELLS WITH A SOURCE FOLLOWER DRIVER IN A SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20120307576
    Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.
    Type: Application
    Filed: August 10, 2012
    Publication date: December 6, 2012
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Memory device program window adjustment
    Patent number: 8307152
    Abstract: In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: November 6, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jonathan Pabustan, Jung-Sheng Hoei
  • SOFT LANDING FOR DESIRED PROGRAM THRESHOLD VOLTAGE
    Publication number: 20120275233
    Abstract: Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.
    Type: Application
    Filed: July 12, 2012
    Publication date: November 1, 2012
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jung-Sheng Hoei, Jonathan Pabustan
  • Macro and command execution from memory array
    Patent number: 8291272
    Abstract: Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: October 16, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Benjamin Louie
  • Programming error correction code into a solid state memory device with varying bits per cell
    Patent number: 8291271
    Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: October 16, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • Expanded programming window for non-volatile multilevel memory cells
    Patent number: 8289776
    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel memory cells. One method includes associating a different logical state with each of a number of different threshold voltage (Vt) distributions. In various embodiments, at least two Vt distributions include negative Vt levels. The method includes applying a read voltage to a word line of a selected cell while applying a pass voltage to word lines of unselected cells, applying a boost voltage to a source line coupled to the selected cell, applying a voltage greater than the boost voltage to a bit line of the selected cell, and sensing a current variation of the bit line in response to the selected cell changing from a non-conducting state to a conducting state.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: October 16, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung Sheng Hoei, Frankie F. Roohparvar
  • NON-VOLATILE MEMORY DEVICE HAVING ASSIGNABLE NETWORK IDENTIFICATION
    Publication number: 20120246396
    Abstract: Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller.
    Type: Application
    Filed: June 7, 2012
    Publication date: September 27, 2012
    Inventor: Frankie F. ROOHPARVAR
  • MEMORY DEVICES AND THEIR OPERATION WITH DIFFERENT SETS OF LOGICAL ERASE BLOCKS
    Publication number: 20120243316
    Abstract: Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a first size the logical erase blocks of the second set of logical erase blocks each have a second size different than the first size.
    Type: Application
    Filed: June 11, 2012
    Publication date: September 27, 2012
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Frankie F. Roohparvar
  • Mitigation of runaway programming of a memory device
    Patent number: 8274835
    Abstract: Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided. In one such method, a ramp voltage signal is generated by a digital count signal. A memory cell being program verified is turned on by a particular verify voltage of the ramp voltage signal in response to a digital count of the digital count signal. The memory cell turning on generates a bit line indication that causes the digital count to be compared to a representation of the target data to be programmed in the memory cell. The comparator circuit generates an indication when the digital count is greater than or equal to the target data.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jonathan Pabustan, Frankie F. Roohparvar
  • Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device
    Patent number: 8274833
    Abstract: A write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. A read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Methods and apparatus utilizing expected coupling effect in the programming of memory cells
    Patent number: 8274823
    Abstract: Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be utilized to tighten the distribution of threshold voltages for a given bit pattern by compensating for anticipated threshold voltage shift due to capacitive coupling, which can facilitate more discernable Vt ranges, and thus a higher number of bits of data per memory cell. Tightening the distribution of threshold voltages can further facilitate wider margins between Vt ranges, and thus an increased reliability in reading the correct data value of a memory cell.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin
  • Coarse and fine programming in a solid state memory
    Patent number: 8259491
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: September 4, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • INCREASED NAND FLASH MEMORY READ THROUGHPUT
    Publication number: 20120221780
    Abstract: A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches.
    Type: Application
    Filed: May 7, 2012
    Publication date: August 30, 2012
    Applicant: Round Rock Research, LLC
    Inventors: Dzung H. Nguyen, Frankie F. Roohparvar