Patents by Inventor Frankie F. Roohparvar

Frankie F. Roohparvar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adjusting for charge loss in a memory
    Patent number: 8174887
    Abstract: Memory and methods of operating a memory adjusting an output voltage of an analog storage device, such as a data cache capacitor holding a voltage level representative of data, in response to an estimated charge loss are useful for compensating for the effects of charge leakage from the analog storage devices.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: May 8, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL
    Publication number: 20120106249
    Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
    Type: Application
    Filed: January 9, 2012
    Publication date: May 3, 2012
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • MACRO AND COMMAND EXECUTION FROM MEMORY ARRAY
    Publication number: 20120110375
    Abstract: Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation.
    Type: Application
    Filed: January 9, 2012
    Publication date: May 3, 2012
    Inventors: Frankie F. ROOHPARVAR, Benjamin Louie
  • NAND flash content addressable memory
    Patent number: 8169808
    Abstract: NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In addition, the NAND architecture non-volatile CAM memory operates with reduced power consumption characteristics for low power and portable applications. In one NAND architecture non-volatile CAM memory embodiment a wired NOR match line array is utilized. In another embodiment a NAND match line array is shown. In yet other embodiments, hierarchal addressing, hash addressing, tree search and algorithmic/hardware engine based search is detailed utilizing both conventional NAND architecture non-volatile Flash memory arrays and dedicated NAND architecture CAM arrays utilizing wired NOR and wired NAND match lines.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: May 1, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Cell operation monitoring
    Patent number: 8159874
    Abstract: Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Atypical cell, block, string, column, row, etc. . . . operation is monitored and locations and type of atypical operation stored. Adjustment of operation is performed based upon the atypical cell operation.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: April 17, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • N WELL IMPLANTS TO SEPARATE BLOCKS IN A FLASH MEMORY DEVICE
    Publication number: 20120081968
    Abstract: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.
    Type: Application
    Filed: December 13, 2011
    Publication date: April 5, 2012
    Inventor: Frankie F. Roohparvar
  • NON-VOLATILE MEMORY DEVICE HAVING ASSIGNABLE NETWORK IDENTIFICATION
    Publication number: 20120084493
    Abstract: Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller.
    Type: Application
    Filed: December 9, 2011
    Publication date: April 5, 2012
    Inventor: Frankie F. ROOHPARVAR
  • PROGRAMMING A MEMORY DEVICE TO INCREASE DATA RELIABILITY
    Publication number: 20120075933
    Abstract: Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group of memory cells of the array having a relative reliability corresponding to the target reliability.
    Type: Application
    Filed: November 29, 2011
    Publication date: March 29, 2012
    Inventor: Frankie F. ROOHPARVAR
  • SENSING OF MEMORY CELLS IN NAND FLASH
    Publication number: 20120075929
    Abstract: An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash memory array is read by applying an elevated voltage to the source line, an elevated pass voltage (Vpass) is placed on the gates of the unselected cells of the string to place them in a pass through mode of operation, and a read gate voltage (Vg) is applied to the gate of the selected cell. The selected memory cell operates as a source follower to set a voltage on the coupled bit line at the read gate voltage minus the threshold voltage of the cell (Vg?Vt), allowing the voltage of the cell to be directly sensed or sampled.
    Type: Application
    Filed: December 5, 2011
    Publication date: March 29, 2012
    Inventors: Frankie F. ROOHPARVAR, Vishal Sarin
  • REDUCING NOISE IN SEMICONDUCTOR DEVICES
    Publication number: 20120069675
    Abstract: The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.
    Type: Application
    Filed: December 1, 2011
    Publication date: March 22, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jung Sheng Hoei
  • MEMORY DEVICE WITH USER CONFIGURABLE DENSITY/PERFORMANCE
    Publication number: 20120072653
    Abstract: The memory device is comprised of a memory array having a plurality of memory cells that are organized into memory blocks. Each memory cell is capable of storing a selectable quantity of data bits (e.g., multiple level cells or a single bit per cell). Control circuitry controls the density configuration of read or write operations to the memory blocks in response to a configuration command. In one embodiment, the configuration command is part of the read or write command. In another embodiment, the configuration command is read from a configuration register.
    Type: Application
    Filed: November 29, 2011
    Publication date: March 22, 2012
    Inventor: Frankie F. Roohparvar
  • READING DATA FROM MEMORY CELLS INCLUDING STORING CHARGES TO ANALOG STORAGE DEVICES
    Publication number: 20120063225
    Abstract: Methods of reading data from memory cells. Such methods include subjecting an analog storage device to a voltage level indicative of a threshold voltage of a memory cell to store a charge to the analog storage device, and generating an analog voltage from the stored charge.
    Type: Application
    Filed: November 21, 2011
    Publication date: March 15, 2012
    Inventor: Frankie F. Roohparvar
  • Apparatus and methods for programming multilevel-cell NAND memory devices
    Patent number: 8134872
    Abstract: Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the first memory cell. If the attempt to add the second data value to the first memory cell is unsuccessful, the first data value and the second data value are written to one or more other memory cells.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: March 13, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • ANALOG READ AND WRITE PATHS IN A SOLID STATE MEMORY DEVICE
    Publication number: 20120057408
    Abstract: A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.
    Type: Application
    Filed: November 14, 2011
    Publication date: March 8, 2012
    Inventors: Frankie F. Roohparvar, Vishal Sarin
  • Programming memory cells with additional data for increased threshold voltage resolution
    Patent number: 8127091
    Abstract: Methods for data transfer and/or programming a memory device, memory devices and memory systems are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar
  • Sensing against a reference cell
    Patent number: 8125831
    Abstract: Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include programming to a target threshold voltage within a range representative of the desired bit pattern. Reading such memory devices can include generating an analog data signal indicative of a threshold voltage of a target memory cell. The target memory cell can be sensed against a reference cell includes a dummy string of memory cells connected to a target string of memory cells, and, such as by using a differential amplifier to sense a difference between a reference cell and the target cell. This may allow a wider range of voltages to be used for data states.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin
  • Memory device program window adjustment
    Patent number: 8117375
    Abstract: In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: February 14, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar, Jonathan Pabustan, Jung-Sheng Hoei
  • M+N bit programming and M+L bit read for M bit memory cells
    Patent number: 8111550
    Abstract: A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: February 7, 2012
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS
    Publication number: 20120030529
    Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 2, 2012
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
  • DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE
    Publication number: 20120026816
    Abstract: During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal operation of the memory device. In one embodiment, the memory test is for a programmability test to determine if the memory block can be programmed. An indication of programmability is stored in each block in a predetermined location.
    Type: Application
    Filed: October 7, 2011
    Publication date: February 2, 2012
    Inventor: Frankie F. Roohparvar