Patents by Inventor Frankie F. Roohparvar

Frankie F. Roohparvar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MULTIPLE LEVEL CELL MEMORY DEVICE WITH SINGLE BIT PER CELL, RE-MAPPABLE MEMORY BLOCK
    Publication number: 20140115383
    Abstract: A system having a non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Blocks can operate in either a multiple bit per cell mode or a single bit per cell mode. A processor controls the system and selects blocks to operate in the multiple bit per cell mode and single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode.
    Type: Application
    Filed: December 24, 2013
    Publication date: April 24, 2014
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Frankie F. Roohparvar
  • Refresh of non-volatile memory cells based on fatigue conditions
    Patent number: 8707112
    Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
  • PROGRAMMING BASED ON CONTROLLER PERFORMANCE REQUIREMENTS
    Publication number: 20140104944
    Abstract: Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit.
    Type: Application
    Filed: December 16, 2013
    Publication date: April 17, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Frankie F. ROOHPARVAR, Vishal SARIN, Jung-Sheng HOEI
  • PROGRAMMING METHODS AND MEMORIES
    Publication number: 20140104958
    Abstract: Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.
    Type: Application
    Filed: December 17, 2013
    Publication date: April 17, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Vishal SARIN, William H. RADKE, Frankie F. ROOHPARVAR
  • Memory controller self-calibration for removing systemic influence
    Patent number: 8693246
    Abstract: Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
  • Processors for programming multilevel-cell NAND memory devices
    Patent number: 8693251
    Abstract: In an embodiment, a processor includes a storage device. The processor is configured to request first data from a first location of a memory device. The storage device is configured to receive and to store the first data from the memory device. The processor is configured to attempt to write second data to the first location of the memory device. The processor is configured to write the first data stored in the storage device and the second data to one or more other locations of the memory device if the attempt to write second data to the first location of the memory device fails.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Programming methods and memories
    Patent number: 8687431
    Abstract: Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, William H. Radke, Frankie F. Roohparvar
  • Analog sensing of memory cells with a source follower driver in a semiconductor memory device
    Patent number: 8687430
    Abstract: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • MEMORY DEVICES AND THEIR OPERATION WITH DIFFERENT SETS OF LOGICAL ERASE BLOCKS
    Publication number: 20140085980
    Abstract: Systems comprising an array of memory cells organized into a plurality of erasable physical blocks, the address of physical block associated with an array of memory cells having a predetermined logical erase block size, wherein at least of the logical erase block size is smaller than another logical erase block size and a processor that selects the storage of data among different logical erase blocks in the array of memory cells based upon programmable and predetermined criteria.
    Type: Application
    Filed: December 2, 2013
    Publication date: March 27, 2014
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Frankie F. Roohparvar
  • Non-volatile memory device adapted to identify itself as a boot memory
    Patent number: 8677109
    Abstract: Non-volatile memory devices and methods of their operation are provided. One such non-volatile memory device has an interface and a control circuit. The non-volatile memory device is adapted to identify itself as a boot memory in response to receiving an interrogation request on the interface.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: March 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Cliff Zitlaw, Frankie F. Roohparvar, David Eggleston
  • PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL
    Publication number: 20140053033
    Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
    Type: Application
    Filed: October 17, 2013
    Publication date: February 20, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS
    Publication number: 20140040683
    Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.
    Type: Application
    Filed: October 4, 2013
    Publication date: February 6, 2014
    Applicant: Mocron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • Cell deterioration warning apparatus and method
    Patent number: 8644070
    Abstract: Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Warning of cell deterioration can be performed using reference cells programmed in accordance with a known pattern such as to approximate deterioration of non-volatile memory cells of the device.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: February 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Memory system with user configurable density/performance option
    Patent number: 8644065
    Abstract: The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple memory blocks. The different memory blocks of each die can be assigned a different memory density by the end user, depending on the desired memory performance and/or memory density. The user configurable density/performance option can be adjusted with special read/write operations or a configuration register having a memory density configuration bit for each memory block.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: February 4, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • MACRO AND COMMAND EXECUTION FROM MEMORY ARRAY
    Publication number: 20140026005
    Abstract: Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation.
    Type: Application
    Filed: September 23, 2013
    Publication date: January 23, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Frankie F. ROOHPARVAR, Benjamin LOUIE
  • Programming a memory device to increase data reliability
    Patent number: 8630122
    Abstract: Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group of memory cells of the array having a relative reliability corresponding to the target reliability.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: January 14, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Multiple level cell memory device with single bit per cell, re-mappable memory block
    Patent number: 8625346
    Abstract: A system having a non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Blocks can operate in either a multiple bit per cell mode or a single bit per cell mode. A processor controls the system and selects blocks to operate in the multiple bit per cell mode and single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: January 7, 2014
    Assignee: Round Rock Research, LLC
    Inventor: Frankie F. Roohparvar
  • Programming based on controller performance requirements
    Patent number: 8611149
    Abstract: A solid state drive is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, including an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: December 17, 2013
    Assignee: Micron Technology
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • Memory devices and their operation with different sets of logical erase blocks
    Patent number: 8605515
    Abstract: Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a first size the logical erase blocks of the second set of logical erase blocks each have a second size different than the first size.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: December 10, 2013
    Assignee: Round Rock Research, LLC
    Inventor: Frankie F. Roohparvar
  • PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY
    Publication number: 20130314993
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate.
    Type: Application
    Filed: August 5, 2013
    Publication date: November 28, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar