Abstract: A flash memory device having a mini array to store operating parameters. In one embodiment, the flash memory device comprises at least one array block of memory, one or more local latches to store one or more operating parameters and a mini array of non-volatile memory cells. The mini array is used to store the one or more operating parameters. During operation of the flash memory device, the one or more operating parameters are retrieved from the mini array and stored in associated local latches.

Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible READ interface. The memory device employs a virtual paging scheme that allows for the architecture of the memory to implement an efficient Flash memory structure internally. Externally, the memory logically maps the internal Flash architecture to an SDRAM compatible interface and virtual architecture, allowing for memory access and operation with a compatible SDRAM controller device. Programming, erasing, block protection, and other Flash specific functions differ from SDRAM and are performed with an SDRAM command sequence. A memory device may have four times as many rows in a memory array bank as a comparable SDRAM device, but only one fourth as many columns. This reduces the number of sense amplifiers activating, therefore saving power and complexity in the memory device.

Abstract: An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device employs a virtual paging scheme that allows for the architecture of the memory to implement an efficient Flash memory structure internally. Externally, the memory logically maps the internal Flash architecture to an SDRAM compatible interface and virtual architecture, allowing for memory access and operation with a compatible SDRAM controller device. A double data rate interface is provided to allow data to be input and output from the memory in synchronization with both rising and falling edges of a clock signal.

Abstract: An improved Flash memory device with a synchronous interface has been detailed that enhances initialization of the Flash memory device. In the prior art, initialization of synchronous Flash memory requires the release of hardware signal line, RP#, or an initialization command, LCR, and a following initialization time wait period of 50 &mgr;S to 100 &mgr;S. The improved Flash memory device of the detailed invention begins initialization of internal values upon acquiring stable power. The initialization cycle of the detailed synchronous Flash memory loops and continues until a “STOP” command is received from the host controller and is immediately available for access. This allows the utilization of the detailed synchronous Flash memory in systems wherein the host controller cannot supply an initializing signal (RP# or LCR).

Abstract: A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between longer run interconnect lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing on the remaining interconnect lines and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without critically increasing the line-to-line capacitance of these lines and adversely affecting the overall line RC time constant.

Abstract: A method of erasing a memory cell includes the step of erasing a memory cell. The current in the memory cell is measured. If the measured memory cell current approximately exceeds a predetermined level, the memory cell is soft programmed so if the memory cell is not overerased, the memory cell is undisturbed. The memory cell is soft programmed until the measured memory cell current is less than or equal to the predetermined level.

Abstract: A memory device is provided. The memory device has a memory array and control circuitry to control operations to the memory array. A redundant register having a bit is also included. The bit is at a first level when two rows of the memory array are shorted together or at a second level when four rows of the memory array are shorted together. The control circuitry instructs an address counter, during an erase operation, to increment row addresses of the rows of the memory array by two rows when the bit is at the first level or four rows when the bit is at the second level.

Abstract: A memory device is described which includes a latch circuit for latching a normally externally provided signal during a test mode. The input pin which is normally enabled to receive the external signal is re-routed to provide an external reference voltage, Vref, to internal circuitry. During testing operations the external Vref signal is used. Once an integrated circuit is determined to be good, an internal generator circuit is set to provide Vref. The integrated circuit can be a flash memory device, and the input pin can be a BYTE command pin. This method of substituting the source of Vref eliminates time required to set the internal generator circuit in defective memory devices.

Abstract: An integrated circuit includes trim circuitry to control operations of internal circuitry. The integrated circuit includes multiplex circuitry for coupling the trim circuitry to internal circuits via a trim bus in a manner which reduces die area. The trim circuitry is controlled such that fuses used to control different level and timing parameters are grouped together and routed across the integrated circuit using the trim bus and multiplex circuit.

Abstract: An apparatus which allows the pulse duration of the high voltage pulses used in the programming and erase operations of a non-volatile memory system to be determined by an external timing signal instead of the internal timer normally used. Control of the pulse duration by the internal timer is disabled by gating the timer output signal with the external signal in a manner such that the gate output signal (which triggers the end of the high voltage pulse) is only generated when the external timing signal has a predetermined value. By controlling the value of the external timing signal, the pulse duration can be varied and have values other than those which would result from use of the internal timer.

Abstract: A state machine and its associated method for achieving a faster response time for an interruption of an erase operation is disclosed. In particular, a state machine having a plurality of interconnected execution cycles is disclosed. The execution cycles include incremental cycles and other cycles. The state machine also includes a plurality of suspend cycles. Each suspend cycle is connected directly to one of the execution cycles. At least one of the suspend cycles is connected directly to one of the other cycles.

Abstract: A flash memory is described which uses floating gate transistors as memory cells. A source regulation circuit within the memory is described which generates a ramped reference voltage signal. The ramped reference voltage signal is applied to a differential amplifier connected to a reference circuit to produce a ramped erase voltage signal. The ramped erase voltage signal is then applied to sources of the memory cells during an erase operation. Both analog and digital circuits are described for generating the ramped reference voltage signal.

Abstract: An integrated circuit includes trim circuitry to control operations of internal circuitry. The integrated circuit includes multiplex circuitry for coupling the trim circuitry to internal circuits via a trim bus in a manner which reduces die area. The trim circuitry is controlled such that fuses used to control different level and timing parameters are grouped together and routed across the integrated circuit using the trim bus and multiplex circuit.

Abstract: A method and apparatus for using a supply signal, rather than a programming signal, to test bitline stress and multicolumn programming in semiconductor memory devices is disclosed. The memory device includes a bitline driver that controls the voltage on the bitline. The method has the step of generating a programming signal and a supply signal. Both the programming signal and the supply signal are suitable for powering the memory device. The supply signal is provided to the bitline driver during the test-programming of the memory device. The memory device includes a bitline driver circuit which provides an output to a data line. The circuit isolates the programming signal from the data line, and the supply signal is placed in electrical communication with the data line.

Abstract: A method of erasing a memory cell includes the step of erasing a memory cell. The current in the memory cell is measured. If the measured memory cell current approximately exceeds a predetermined level, the memory cell is soft programmed so if the memory cell is not overerased, the memory cell is undisturbed. The memory cell is soft programmed until the measured memory cell current is less than or equal to the predetermined level.

Abstract: An integrated circuit includes trim circuitry to control operations of internal circuitry. The integrated circuit includes multiplex circuitry for coupling the trim circuitry to internal circuits via a trim bus in a manner which reduces die area. The trim circuitry is controlled such that fuses used to control different level and timing parameters are grouped together and routed across the integrated circuit using the trim bus and multiplex circuit.

Abstract: A method of soft programming a block of memory cells includes the step of measuring current in a bit line of a column in the block. If the measured bit line current exceeds a predetermined level, memory cells coupled to the bit line are sequentially soft programmed for approximately a predetermined period of time so non-overerased memory cells are undisturbed, and until the measured bit line current is less than or equal to a predetermined level.

Abstract: A flash memory is described which uses floating gate transistors as memory cells. A source regulation circuit within the memory is described which generates a ramped reference voltage signal. The ramped reference voltage signal is applied to a differential amplifier connected to a reference circuit to produce a ramped erase voltage signal. The ramped erase voltage signal is then applied to sources of the memory cells during an erase operation. Both analog and digital circuits are described for generating the ramped reference voltage signal.

Abstract: A memory device is described which includes a latch circuit for latching a normally externally provided signal during a test mode. The input pin which is normally enabled to receive the external signal is re-routed to provide an external reference voltage, Vref, to internal circuitry. During testing operations the external Vref signal is used. Once an integrated circuit is determined to be good, an internal generator circuit is set to provide Vref. The integrated circuit can be a flash memory device, and the input pin can be a BYTE command pin. This method of substituting the source of Vref eliminates time required to set the internal generator circuit in defective memory devices.

Abstract: A method and apparatus for using a supply signal, rather than a programming signal, to test bitline stress and multicolumn programming in semiconductor memory devices is disclosed. The memory device includes a bitline driver that controls the voltage on the bitline. The method has the step of generating a programming signal and a supply signal. Both the programming signal and the supply signal are suitable for powering the memory device. The supply signal is provided to the bitline driver during the test-programming of the memory device. The memory device includes a bitline driver circuit which provides an output to a data line. The circuit isolates the programming signal from the data line, and the supply signal is placed in electrical communication with the data line.