Abstract: A flash memory is described which uses floating gate transistors as memory cells. A source regulation circuit within the memory is described which generates a ramped reference voltage signal. The ramped reference voltage signal is applied to a differential amplifier connected to a reference circuit to produce a ramped erase voltage signal. The ramped erase voltage signal is then applied to sources of the memory cells during an erase operation. Both analog and digital circuits are described for generating the ramped reference voltage signal.

Abstract: A method of the present invention includes the step of applying a drain pulse to a drain of a flash cell. A gate pulse is applied to a control gate of the flash cell coincident with the drain pulse. The amplitude of the gate pulse is varied between a maximum and a diminished amplitude to form a series of modulated gate pulses. The modulated gate pulses have substantially similar maximum and diminished amplitudes. A width of a modulated gate pulse is substantially lower than a width of the drain pulse. An apparatus of the present invention includes a flash cell having a control gate, a floating gate, a drain, and a channel. A switchable charge pump is coupled to the control gate, and generates a modulated gate pulse. A power supply is coupled to the drain and generates a drain pulse. The modulated gate pulse is coupled to the control gate coincidently when the drain pulse is coupled to the drain. The width of the modulated gate pulse is substantially lower than the width of the drain pulse.

Abstract: A state machine and its associated method for achieving a faster response time for an interruption of an erase operation is disclosed. In particular, a state machine having a plurality of interconnected execution cycles is disclosed. The execution cycles include incremental cycles and other cycles. The state machine also includes a plurality of suspend cycles. Each suspend cycle is connected directly to one of the execution cycles. At least one of the suspend cycles is connected directly to one of the other cycles.

Abstract: A method and apparatus for using a supply signal, rather than a programming signal, to test bitline stress and multicolumn programming in semiconductor memory devices is disclosed. The memory device includes a bitline driver that controls the voltage on the bitline. The method has the step of generating a programming signal and a supply signal. Both the programming signal and the supply signal are suitable for powering the memory device. The supply signal is provided to the bitline driver during the test-programming of the memory device. The memory device includes a bitline driver circuit which provides an output to a data line. The circuit isolates the programming signal from the data line, and the supply signal is placed in electrical communication with the data line.

Abstract: A flash memory is described which includes circuitry to determine how many memory cells can be programmed in a single write operation by measuring the power available for programming. The available power is determined by monitoring Vcc and/or Vpp prior to performing a data write operation. The memory control circuit adjusts the memory write operation based upon the actual operating conditions and is not limited in performance to anticipated specification limits. A method is described which reduces the number of total write operations by performing a limited number rewrites in place of individual rewrite operations by rewriting only memory cells which where not properly programmed. Rewrite operations of properly programmed memory cells is avoided to reduce the total number of write operations.

Abstract: A method of the present invention includes the step of applying a drain pulse to a drain of a flash cell. A gate pulse is applied to a control gate of the flash cell coincident with the drain pulse. The amplitude of the gate pulse is varied between a maximum and a diminished amplitude to form a series of modulated gate pulses. The modulated gate pulses have substantially similar maximum and diminished amplitudes. A width of a modulated gate pulse is substantially lower than a width of the drain pulse. An apparatus of the present invention includes a flash cell having a control gate, a floating gate, a drain, and a channel. A switchable charge pump is coupled to the control gate, and generates a modulated gate pulse. A power supply is coupled to the drain and generates a drain pulse. The modulated gate pulse is coupled to the control gate coincidently when the drain pulse is coupled to the drain. The width of the modulated gate pulse is substantially lower than the width of the drain pulse.

Abstract: A flash memory is described which includes circuitry to determine how many memory cells can be programmed in a single write operation by measuring the power available for programming. The available power is determined by monitoring Vcc and/or Vpp prior to performing a data write operation. The memory control circuit adjusts the memory write operation based upon the actual operating conditions and is not limited in performance to anticipated specification limits. A method is described which reduces the number of total write operations by performing a limited number rewrites in place of individual rewrite operations by rewriting only memory cells which where not properly programmed. Rewrite operations of properly programmed memory cells is avoided to reduce the total number of write operations.

Abstract: A parallel processing redundancy memory circuit. The circuit includes parallel data paths for regular memory columns and redundant columns. An input/output buffer is coupled to the parallel paths and receives I/O selection bits. In operation, address drivers simultaneously access both the regular memory and the redundant columns. The input/output buffer then selects the appropriate data path, as determined by the I/O selection bits, for writing or reading data.

Abstract: A filtered command port architecture for a memory array is disclosed. A command controller is directly connected to the memory array and receives command instructions from an external microprocessor via an address and data bus. A command clock is used to latch commands from the data bus into a command decoder. A timing signal is used to filter incoming signals from the data bus which are asserted for less than a predetermined amount of time. A state decoder then tracks a sequence of commands from the command decoder and performs an appropriate action in response to the commands.