Abstract: The invention relates to an semi-conductor device comprising a first surface and neighboring first and second electric elements arranged on the first surface, in which each of the first and second elements extends from the first surface in a first direction, the first element having a cross section substantially perpendicular to the first direction and a sidewall surface extending at least partially in the first direction, wherein the sidewall surface comprises a first section and a second section adjoining the first section along a line extending substantially parallel to the first direction, wherein the first and second sections are placed at an angle with respect to each other for providing an inner corner wherein the sidewall surface at the inner corner is, at least partially, arranged at a constant distance R from a facing part of the second element for providing a mechanical reinforcement structure at the inner corner.

Abstract: An integration substrate for a system in package comprises a through-substrate via and a trench capacitor wherein with a trench filling that includes at least four electrically conductive capacitor-electrode layers in an alternating arrangement with dielectric layers. —The capacitor-electrode layers are alternatingly connected to a respective one of two capacitor terminals provided on the first or second substrate side. The trench capacitor and the through-substrate via are formed in respective trench openings and via openings in the semiconductor substrate, which have an equal lateral extension exceeding 10 micrometer. This structure allows, among other advantages, a particularly cost-effective fabrication of the integration substrate because the via openings and the trench openings in the substrate can be fabricated simultaneously.

Abstract: An electronic device is provided which comprises a DC-DC converter. The DC-DC converter comprises at least one solid-state rechargeable battery (B1, B2) for storing energy for the DC-DC conversion and an output capacitor (C2).

Abstract: An electronic device comprising at least one die stack having at least a first die (D1) comprising a first array of light emitting units (OLED) for emitting light, a second layer (D2) comprising a second array of via holes (VH) and a third die (D3) comprising a third array of light detecting units (PD) for detecting light from the first array of light emitting units (OELD) is provided. The second layer (D2) is arranged between the first die (D1) and the third die (D3). The first, second and third array are aligned such that light emitted from the first array of light emitting units (OLED) passed through the second array of via holes (VH) and is detected by the third array of light detecting units (PD). The first array of light emitting units and/or the third array of light detecting units are manufactured based on standard semiconductor manufacturing processes.

Abstract: A method of fabricating a trench capacitor, and a trench capacitor fabricated thereby, are disclosed. The method involves the use of a vacuum impregnation process for a sol-gel film, to facilitate effective deposition of high-permittivity materials within a trench in a semiconductor substrate, to provide a trench capacitor having a high capacitance while being efficient in utilization of semiconductor real estate.

Abstract: A method of plating via hole in a substrate includes providing a substrate having a first side and a second side and a plurality of through substrate via holes; depositing a first seed layer on the first side of the substrate; applying a foil on the first seed layer of the substrate closing the first ends of the plurality of via holes; electro-chemical plating of the second side of the substrate; and removing the foil.

Abstract: The invention relates to an apparatus for reactive ion etching of a substrate, comprising: a plasma etch zone including an etch gas supply and arranged with a plasma generating structure for igniting a plasma and comprising an electrode structure arranged to accelerate the etch plasma toward a substrate portion to have ions impinge on the surface of the substrate; a passivation zone including a cavity provided with a passivation gas supply; said supply arranged for providing a passivation gas flow from the supply to the cavity; the cavity in use being bounded by the injector head and the substrate surface; and a gas purge structure comprising a gas exhaust arranged between said etch zone and passivation zone; the gas purge structure thus forming a spatial division of the etch and passivation zones.

Abstract: Method of depositing an atomic layer on a substrate. The method comprises supplying a precursor gas from a precursor-gas supply of a deposition head that may be part of a rotatable drum. The precursor gas is provided from the precursor-gas supply towards the substrate. The method further comprises moving the precursor-gas supply by rotating the deposition head along the substrate which in its turn is moved along the rotating drum.

Abstract: The present invention relates to a configurable trench multi-capacitor device comprising a trench in a semiconductor substrate. The trench has a lateral extension exceeding 10 micrometer and a trench filling includes a number of at least four electrically conductive capacitor-electrode layers. A switching unit is provided that comprises a plurality of switching elements electrically interconnected between different capacitor-electrode layers of the trench filling. A control unit is connected with the switching unit and configured to generate and provide to the switching unit respective control signals for forming a respective one of a plurality of multi-capacitor configurations using the capacitor-electrode layers of the trench filling.

Abstract: A semiconductor device and a method for manufacturing such semiconductor device for use in a stacked configuration of the semiconductor device are disclosed. The semiconductor device includes a substrate including at least part of an electronic circuit provided at a first side thereof. The substrate includes a passivation layer and a substrate via that extends from the first side to a via depth such that it is reconfigurable into a through-substrate. The semiconductor device further includes a patterned masking layer on the first side of the substrate. The patterned masking layer includes a trench extending fully through the patterned masking layer. The trench has been filled with a redistribution conductor. The substrate via and the redistribution conductor include metal paste and together form one piece, such that there is no physical interface between the through-substrate via and the redistribution conductor. Thus, the parasitic resistance of this electrical connection is reduced.

Abstract: The present invention provides a means to integrate planar coils on silicon, while providing a high inductance. This high inductance is achieved through a special back- and front sided shielding of a material. In many applications, high-value inductors are a necessity. In particular, this holds for applications in power management. In these applications, the inductors are at least 5 of the order of 1 ?H, and must have an equivalent series resistance of less than 0.1?. For this reason, those inductors are always bulky components, of a typical size of 2×2×1 mm 3, which make a fully integrated solution impossible. On the other hand, integrated inductors, which can monolithically be integrated, do exist. However, these inductors suffer either from low inductance values, or 10 very-high DC resistance values.

Abstract: A method of forming a dielectric layer on a further layer of a semiconductor device is disclosed. The method comprises depositing a dielectric precursor compound and a further precursor compound over the further layer, the dielectric precursor compound comprising a metal ion from the group consisting of Yttrium and the Lanthanide series elements, and the further precursor compound comprising a metal ion from the group consisting of group IV and group V metals; and chemically converting the dielectric precursor compound and the further precursor compound into a dielectric compound and a further compound respectively, the further compound self-assembling during said conversion into a plurality of nanocluster nuclei within the dielectric layer formed from the first dielectric precursor compound. The nanoclusters may be dielectric or metallic in nature. Consequently, a dielectric layer is formed that has excellent charge trapping capabilities.

Abstract: The chip comprises a network of trench capacitors and an inductor, wherein the trench capacitors are coupled in parallel with a pattern of interconnects that is designed so as to limit generation of eddy current induced by the inductor in the interconnects. This allows the use of the chip as a portion of a DC-DC converter, that is integrated in an assembly of a first chip and this—second chip. The inductor of this integrated DC-DC converter may be defined elsewhere within the assembly.

Abstract: The invention relates to an electric device including an electric element, the electric element comprising a first electrode (104) having a first surface (106) and a pillar (108), the pillar extending from the first surface in a first direction (110), the pillar having a length measured from the first surface parallel to the first direction, the pillar having a cross section (116) perpendicular to the first direction and the pillar having a sidewall surface (120) enclosing the pillar and extending in the first direction, characterized in—that, the pillar comprises any one of a score (124) and protrusion (122) extending along at least part of the length of the pillar for giving the pillar (108) improved mechanical stability. The electrode allows electrical elements such as capacitors, energy storage devices or diodes to be made with improved properties in a cost effective way.

Abstract: Therefore, a method of plating wafer via holes in a wafer is provided. A substrate (200) having a first and second side and a plurality of wafer via holes (210) is provided. Each via hole comprises a first and second end extending between the first and second side. A first seed layer (220) is deposited on the first side of the 5 wafer (200). A foil (250) is applied on the first seed layer (220) of the wafer closing the first ends of the plurality of wafer via holes (210). The second side of the wafer (200) is electro-chemically plated and the foil (250) is removed.

Abstract: A battery comprises a carrier foil, with solid state battery elements spaced along the foil and mounted on opposite sides of the foil in pairs, with the battery elements of a pair mounted at the same position along the foil. The carrier foil is folded to define a meander pattern with battery element pairs that are adjacent each other along the foil arranged back to back.

Abstract: A microphone comprises a substrate (20), a microphone membrane (10) defining an acoustic input surface and a backplate (11) supported with respect to the membrane with a fixed spacing between the backplate (11) and the membrane (10). A microphone periphery area comprises parallel corrugations (24) in the membrane (10) and backplate (11). By using the same corrugated suspension for both the membrane and the backplate, the sensitivity to body noise is optimally suppressed.

Abstract: An electronic device includes at least one trench capacitor that can also take the form of an inverse structure, a pillar capacitor. An alternating layer sequence of at least two dielectric layers and at least two electrically conductive layers is provided in the trench capacitor or on the pillar capacitor, such that the at least two electrically conductive layers are electrically isolated from each other and from the substrate by respective ones of the at least two dielectric layers. A set of internal contact pads is provided, and each internal contact pad is connected with a respective one of the electrically conductive layers or with the substrate. A range of switching opportunities is opened up that allows tuning the specific capacitance of the capacitor to a desired value.

Abstract: The invention relates to a semiconductor device for use in a stacked configuration of the semiconductor device and a further semiconductor device. The semiconductor device comprises: a substrate (5) comprising at least part of an electronic circuit (7) provided at a first side thereof. The substrate (5) comprises a passivation layer (19) at the first side and a substrate via that extends from the first side to a via depth beyond a depth of the electronic circuit (7) such that it is reconfigurable into a through-substrate via (10) by backside thinning of the substrate (5). The semiconductor device further comprises: a patterned masking layer (15) on the first side of the substrate (5). The patterned masking layer (15) comprises at least a trench (16) extending fully through the patterned masking layer (15). The trench has been filled with a redistribution conductor (20). The substrate via and the redistribution conductor (20) comprise metal paste (MP) and together form one piece.

Abstract: The invention relates to an semi-conductor device comprising a first surface and neighboring first and second electric elements arranged on the first surface, in which each of the first and second elements extends from the first surface in a first direction, the first element having a cross section substantially perpendicular to the first direction and a sidewall surface extending at least partially in the first direction, wherein the sidewall surface comprises a first section and a second section adjoining the first section along a line extending substantially parallel to the first direction, wherein the first and second sections are placed at an angle with respect to each other for providing an inner corner wherein the sidewall surface at the inner corner is, at least partially, arranged at a constant distance R from a facing part of the second element for providing a mechanical reinforcement structure at the inner corner.