Patents by Inventor Fu Chen

Fu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12384015
    Abstract: A telescopic wrench includes an outer tube, an outer sleeve, and an inner rod. The first hole of the outer sleeve ring is fitted onto the outer tube, and the second hole of the outer sleeve provides peripheral contact with the rod section of the inner rod. The outer sleeve forms an external auxiliary fitting structure with the inner rod and outer tube. The telescopic wrench provides an improvement over known structures that are prone to loosening and noise during use. The telescopic wrench enhances the structural strength when subjected to operating forces.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: August 12, 2025
    Inventors: Yi-Fu Chen, He-Qian Chen
  • Publication number: 20250250163
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first movable element over a first substrate. A second movable element overlies the first substrate. A first functional layer is on the first movable element. The first functional layer comprises a first material different from a material of the first movable element. A second functional layer is on the second movable element.
    Type: Application
    Filed: April 25, 2025
    Publication date: August 7, 2025
    Inventors: Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
  • Patent number: 12376621
    Abstract: A cigar cutter with an arresting mechanism includes a pivotally connected arresting block and a guide track divided into a smooth groove, an abutting groove with an abutting block having a portion corresponding to a space between two opposite sides of the smooth groove, and a direction-changing groove having a shoulder opposite to the abutting block and two ends in communication with an end of the smooth groove and an end of the abutting groove, respectively. The arresting block can be moved in the guide track. When the cutter enters a closed state from an open state, the arresting block sequentially touches the abutting block and the shoulder, driving itself to rotate. A length between two opposite sides of a rotated arresting block is greater than two opposite sides of the smooth groove, keeping the arresting block from extending into the smooth groove and the cutter in the closed state.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: August 5, 2025
    Inventor: Shun-Fu Chen
  • Patent number: 12369327
    Abstract: The present disclosure relates to a ferroelectric memory device that includes a bottom electrode, a ferroelectric structure overlying the bottom electrode, and a top electrode overlying the ferroelectric structure where the bottom electrode includes molybdenum.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: July 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Fu-Chen Chang, Tzu-Yu Chen, Sheng-Hung Shih, Kuo-Chi Tu
  • Patent number: 12362270
    Abstract: A package structure includes a first redistribution layer, a semiconductor die, and through vias. The first redistribution layer includes dielectric layers, first conductive patterns, and second conductive patterns. The dielectric layers are located in a core region and a peripheral region of the first redistribution layer. The first conductive patterns are embedded in the dielectric layers in the core region, wherein the first conductive patterns are arranged in the core region with a pattern density that gradually increases or decreases from a center of the core region to a boundary of the core region. The second conductive patterns are embedded in the dielectric layers in the peripheral region. The semiconductor die is disposed on the core region over the first conductive patterns. The through vias are disposed on the peripheral region and electrically connected to the second conductive patterns.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kris Lipu Chuang, Tzu-Sung Huang, Chih-Wei Lin, Yu-fu Chen, Hsin-Yu Pan, Hao-Yi Tsai
  • Publication number: 20250228148
    Abstract: A resistive memory device includes a bottom electrode, a switching layer disposed over the bottom electrode, a top electrode disposed over the switching layer, and an auxiliary layer disposed between the switching layer and one of the top electrode and the bottom electrode. The one of the top electrode and the bottom electrode includes a metal and is a relatively inert electrode in comparison with the other one of the top electrode and the bottom electrode. The auxiliary layer includes a nitride of the metal.
    Type: Application
    Filed: January 4, 2024
    Publication date: July 10, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Chen CHANG, Wen-Ting CHU, Kuo-Chi TU, Sheng-Hung SHIH, Chu-Jie HUANG
  • Patent number: 12356630
    Abstract: A semiconductor device includes a random access memory (RAM) structure and a dielectric layer. The RAM structure is over a substrate and includes a bottom electrode layer, a ferroelectric layer over the bottom electrode layer, and a top electrode layer over the ferroelectric layer. The dielectric layer is over the substrate and laterally surrounds a lower portion of the RAM structure. From a cross-sectional view, the bottom electrode layer of the RAM structure has a lateral portion and a vertical portion, and the vertical portion upwardly extends from the lateral portion to a position higher than a top surface of the dielectric layer.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: July 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Chen Chang, Kuo-Chi Tu, Tzu-Yu Chen, Sheng-Hung Shih
  • Patent number: 12356875
    Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.
    Type: Grant
    Filed: June 4, 2024
    Date of Patent: July 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu
  • Publication number: 20250214108
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A plurality of cavities are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a plurality of movable membranes, and where the movable membranes overlie the cavities, respectively. A plurality of fluid communication channels are disposed in the dielectric structure, where each of the fluid communication channels extend laterally between two neighboring cavities of the cavities, such that each of the cavities are in fluid communication with one another.
    Type: Application
    Filed: February 24, 2025
    Publication date: July 3, 2025
    Inventors: I-Hsuan Chiu, Chia-Ming Hung, Li-Chun Peng, Hsiang-Fu Chen
  • Publication number: 20250208445
    Abstract: A semiconductor photonics device includes an optical modulator structure and a modulator heater structure in one or more dielectric layers of the semiconductor photonics device. An isolation trench is included around the modulator heater structure to reduce the likelihood of damage to the dielectric layer(s) that might otherwise be caused by thermal stress. The isolation trench may include an air gap through the dielectric layer(s), and the air gap surrounds the modulator heater structure in a top-down view of the semiconductor photonics device. The isolation trench reduces the amount of heat absorbed in the dielectric layer(s) in that the isolation trench thermally isolates the modulator heater structure from the dielectric layer(s). This reduces the likelihood of cracking, delamination, and/or another type of damage to the dielectric layer(s) that might otherwise be caused by thermal stress to the dielectric layer(s).
    Type: Application
    Filed: January 4, 2024
    Publication date: June 26, 2025
    Inventors: Fan HU, YingKit Felix TSUI, Hsiang-Fu CHEN, Chia-Ming HUNG
  • Publication number: 20250205863
    Abstract: A torque wrench includes a body portion which as a room and a working member is assembled in the room. The working member includes a rod and a working head protruding from the body portion. A torque sensor is connected to the rod of the working member. A release unit is located in the room of the body portion and movably connected to the rod of the working member. A torque setting unit is located in the room to apply a set torque to the release unit. A controller is connected to the torque wrench and electrically connected to the torque sensor and the torque setting unit. When a force applied to the working member exceeds the set torque, the torque setting unit drives the release unit, causing the working member to be free of force.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Inventors: YI-FU CHEN, HE-QIAN CHEN
  • Patent number: 12341978
    Abstract: An image arrangement method and an image processing system are disclosed. In the method, a video stream is decoded into one or more frames of image. The image is buffered in a message queue. The message queue is defined as a first topic. The image in the message queue is transmitted according to a subscribed target of the first topic. Accordingly, the computation burden may be reduced, and the operation efficiency of multiple models may be improved.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: June 24, 2025
    Assignee: Wistron Corporation
    Inventors: Yu-Chen Yeh, Yen Fu Chen, Min Mao Liu, Kun Te Lin
  • Patent number: 12337441
    Abstract: A socket includes a first section and a second section. The first section is to be connected with a tool. The second section includes an outer face, and a mounting hole is axially defined through the second section and communicates through the first section. The mounting hole includes multiple recesses and multiple sides defined in the inner periphery thereof. The multiple recesses and the multiple sides are located alternatively with each other. Each recess includes a rounded corner formed radially in the inner portion thereof. A triangular groove is formed axially and centrally in each side. The angle between two insides of each groove is smaller than 90 degrees. A rusted or damaged bolt head is engaged with either the rounded corners or the grooves so as to be effectively rotated.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: June 24, 2025
    Inventors: Yi-Fu Chen, He-Qian Chen
  • Patent number: 12328944
    Abstract: An integrated circuit layout includes a first and a second standard cells abutting along a boundary line. The boundary line and a first active region of the first standard cell include a distance D1. A first gate line on the first active region protrudes from the first active region by a length L1. The boundary line and a second active region of the second standard cell include a distance D2. A second gate line on the second active region protrudes from the second active region by a length L2. Two first dummy gate lines and two second dummy gate lines are disposed at two sides of the first active region and the second active region and are away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: June 10, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ruei-Yau Chen, Wei-Jen Wang, Kun-Yuan Wu, Chien-Fu Chen, Chen-Hsien Hsu
  • Publication number: 20250157752
    Abstract: A magnetic suspension keyswitch structure includes a receiving frame and a keycap. The receiving frame includes a keycap receiving hole, a pair of first receiving spaces, and a pair of first magnetic members. The first receiving spaces are formed on two inner walls of the receiving frame. The first magnetic member is fixedly received in the first receiving space. The keycap includes a plurality of side surfaces, a pair of second receiving spaces, and a pair of second magnetic members fixedly received in the second receiving spaces. Through a magnetic force between the first magnetic member and the second magnetic member, a top surface of the keycap is normally higher than a top surface of the receiving frame and in a non-pressed state. When the keycap is pressed downward, the magnetic force provides a recovery force to the keycap.
    Type: Application
    Filed: May 14, 2024
    Publication date: May 15, 2025
    Inventors: JEN-FU CHEN, CHIA-HSIN TSAI, LUNG-CHI LU
  • Patent number: 12301134
    Abstract: An inverter-based comparator, powered between a first supply voltage and a second supply voltage being lower than the first supply voltage, includes a first inverter branch composed of at least one first P-type transistor and at least one first N-type transistor; and a second inverter branch composed of at least one second P-type transistor, at least one second N-type transistor and at least two tuning switches. The first inverter branch and the second inverter branch are configured to compare an input voltage with an internal trigger point, thereby generating a compare voltage at an interconnected node. One of the at least two tuning switches is controlled to isolate the first supply voltage and another is controlled to isolate the second supply voltage to compensate for trigger point shifting.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: May 13, 2025
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Philex Ming-Yan Fan, Yi-Fu Chen, Bo-Rui Chen
  • Publication number: 20250149812
    Abstract: A card edge connector includes: a housing having a mating slot for insertion of an electronic card; plural terminals retained in the housing; a latch mounted at a first longitudinal end of the housing; a movable key received in the housing; and a rod attached to the housing, wherein the latch and the movable key are connected with opposite ends of the rod, and the movable key is pushable downwards to push the rod to move in a longitudinal direction to bring the latch to a locked state.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 8, 2025
    Inventors: KUO-CHUN HSU, MING-YI GONG, YU-CHE HUANG, XUN WU, PO-FU CHEN, WEN-LUNG HSU
  • Publication number: 20250149828
    Abstract: A card edge connector includes: a connector body having a card slot and plural terminals arranged on opposite sides of the card slot; a latch mounted at an end of connector body; and a releasing member including a pair of levers disposed at opposite sides of the connector body and a mover, wherein first ends of the levers are connected with the latch, second ends are connected with the mover, and when the card is inserted into the card slot the mover is pushed to move downwards companied with a downward movement of the second ends and an upward movement of the first ends of the levers, the upward movement of the first ends drive the latch to lock with the card and when the card is pulled out the mover is released from a pressure of the card and reset to unlock the latch from the electronic card.
    Type: Application
    Filed: October 30, 2024
    Publication date: May 8, 2025
    Inventors: KUO-CHUN HSU, MING-YI GONG, WEN-LUNG HSU, XUN WU, PO-FU CHEN
  • Publication number: 20250151384
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound semiconductor layer is formed on a first device region and a second device region of a substrate. A III-V compound barrier layer is formed on the III-V compound semiconductor layer. A lamination structure is formed on the III-V compound barrier layer. The lamination structure includes a p-type doped III-V compound layer and a first mask layer disposed thereon. A patterning process is performed to the lamination structure. A first portion of the lamination structure located above the first device region is patterned by the patterning process. A second portion of the lamination structure located above the second device region is removed by the patterning process. A thickness of the second portion of the lamination structure is greater than a thickness of the first portion of the lamination structure before the patterning process.
    Type: Application
    Filed: December 14, 2023
    Publication date: May 8, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shuo-Lin Hsu, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen
  • Publication number: 20250129994
    Abstract: This disclosure is directed to a heat transfer device and a manufacturing method thereof. The method has steps of: providing a metal powder, firstly sintering the metal powder to form a plurality of sintered balls that each sintered ball has a plurality of first pores; provide a thermally conductive housing, the sintered balls are secondly sintered to form a capillary structure combined with the thermally conductive housing, wherein at least a part of an internal wall of the thermally conductive shell is cover with the sintered balls, a plurality of second pores are defined between the sintered balls, and each first pore is smaller than each second pore; filling a working fluid into the thermally conductive housing; and sealing the thermally conductive housing to define a sealed chamber in the thermally conductive housing, so that the capillary structure and the working fluid are contained in the sealed chamber.
    Type: Application
    Filed: July 31, 2024
    Publication date: April 24, 2025
    Inventors: Chia-Ling CHIN, Shih-An YANG, Yen-Fu CHEN