Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound semiconductor layer is formed on a first device region and a second device region of a substrate. A III-V compound barrier layer is formed on the III-V compound semiconductor layer. A lamination structure is formed on the III-V compound barrier layer. The lamination structure includes a p-type doped III-V compound layer and a first mask layer disposed thereon. A patterning process is performed to the lamination structure. A first portion of the lamination structure located above the first device region is patterned by the patterning process. A second portion of the lamination structure located above the second device region is removed by the patterning process. A thickness of the second portion of the lamination structure is greater than a thickness of the first portion of the lamination structure before the patterning process.

Abstract: A card edge connector includes: a housing having a mating slot for insertion of an electronic card; plural terminals retained in the housing; a latch mounted at a first longitudinal end of the housing; a movable key received in the housing; and a rod attached to the housing, wherein the latch and the movable key are connected with opposite ends of the rod, and the movable key is pushable downwards to push the rod to move in a longitudinal direction to bring the latch to a locked state.

Abstract: A card edge connector includes: a connector body having a card slot and plural terminals arranged on opposite sides of the card slot; a latch mounted at an end of connector body; and a releasing member including a pair of levers disposed at opposite sides of the connector body and a mover, wherein first ends of the levers are connected with the latch, second ends are connected with the mover, and when the card is inserted into the card slot the mover is pushed to move downwards companied with a downward movement of the second ends and an upward movement of the first ends of the levers, the upward movement of the first ends drive the latch to lock with the card and when the card is pulled out the mover is released from a pressure of the card and reset to unlock the latch from the electronic card.

Abstract: This disclosure is directed to a heat transfer device and a manufacturing method thereof. The method has steps of: providing a metal powder, firstly sintering the metal powder to form a plurality of sintered balls that each sintered ball has a plurality of first pores; provide a thermally conductive housing, the sintered balls are secondly sintered to form a capillary structure combined with the thermally conductive housing, wherein at least a part of an internal wall of the thermally conductive shell is cover with the sintered balls, a plurality of second pores are defined between the sintered balls, and each first pore is smaller than each second pore; filling a working fluid into the thermally conductive housing; and sealing the thermally conductive housing to define a sealed chamber in the thermally conductive housing, so that the capillary structure and the working fluid are contained in the sealed chamber.

Abstract: An electronic device for assisting driver in recording images is introduced. In the electronic device, a panoramic camera unit is installed on a transportation vehicle to capture an initial video. A positioning unit detects a real-time location of the transportation vehicle. A database stores scenic spot information including multiple scenic spot locations. An intelligence processing unit receives the initial video and uses artificial intelligence to identify a user's image and an image of the scenic spot to be locked at the scenic spot location. The intelligence processing unit receives the real-time location and determines the direction of travel. The intelligence processing unit reads the scenic spot information and determines a viewing range of the transportation vehicle entering the scenic spot location based on the real-time location and the direction of travel to capture a time period within the viewing range from the initial video and crop a recorded video.

Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity.

Abstract: A memory device and a programming method thereof are provided. The memory device has multiple word lines and a dummy word line set. A word line is selected from the word lines and is applied with a program voltage, and unselected word lines and the dummy word line set are applied with a pass voltage. After programming the selected word line, a program verification is performed on the selected word line. When the selected word line passes the program verification, a high bound and/or low bound check for the threshold voltage distribution of at least one of the dummy word lines is performed. When at least one of the dummy word lines fails in the high bound and/or low bound check, the status of the selected word line is shown as fail or a flag is set thereto.

Abstract: A display device includes a display panel, a first adhesive layer, a diffusion layer, and an anti-glare film. The first adhesive layer is disposed on the display panel. The first adhesive layer is disposed between the display panel and the diffusion layer. The anti-glare film is disposed on the diffusion layer, wherein a thickness of the diffusion layer is greater than or equal to 15 microns.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.

Abstract: The quality of a frame sequence is enhanced by a booster engine collaborating with a first stage circuit. The first stage circuit adjusts the quality degradation of the frame sequence when a condition in constrained resources is detected. The quality degradation includes at least one of uneven resolution and uneven frame per second (FPS). The booster engine receives the frame sequence from the first stage circuit, and generates an enhanced frame sequence based on the frame sequence for transmission to a second stage circuit.

Abstract: A semiconductor device comprises an epitaxial layer, a first trench, a first field plate, a first trench gate, a first planar gate, and a first conductive connection portion. The first trench is disposed in the epitaxial layer and extends along a first direction. The first field plate is disposed in the first trench and extends along the first direction. The first trench gate is disposed in the first trench and extends along the first direction, where the first trench gate is laterally separated from the first field plate. The first planar gate is disposed on the first field plate and the first trench gate. The first conductive connection portion is disposed in the first trench and located between the first trench gate and the first planar gate, and the first trench gate is electrically connected to the first planar gate through the first conductive connection portion.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A plurality of cavities are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a plurality of movable membranes, and where the movable membranes overlie the cavities, respectively. A plurality of fluid communication channels are disposed in the dielectric structure, where each of the fluid communication channels extend laterally between two neighboring cavities of the cavities, such that each of the cavities are in fluid communication with one another.

Abstract: An optical package structure is provided. The optical package structure includes a carrier, an optical emitter, an optical receiver, an optical barrier, and an insulating structure. The optical emitter and the optical receiver are over the carrier. The optical barrier is over the carrier and between the optical emitter and the optical receiver, wherein the optical barrier defines a cavity. The insulating structure is filled in the cavity, wherein an elevation of a top surface of the insulating structure is lower than an elevation of a top surface of the optical barrier with respect to a surface of the carrier.

Abstract: A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.

Abstract: A semiconductor device includes a substrate with first conductivity type and an epitaxial layer; a first trench and a second trench in the epitaxial layer, the depth of the first trench being greater than that of the second trench; a first gate structure including a first gate in the first trench and a first gate dielectric layer; a second gate structure including a second gate in the second trench and a second gate dielectric layer between the second gate and the epitaxial layer; a body region with second conductivity type being spaced apart from the first gate dielectric layer and being contiguous with the second gate dielectric layer; a first electrode region having first conductivity type; a third gate structure on the epitaxial layer and partially overlapping with the body region; and a second electrode. The Avalanche Energy, Single Pulse (EAS) durability of the semiconductor device is improved.

Abstract: A semiconductor device includes a substrate of first conductive type and an epitaxial layer; a first trench in the epitaxial layer; a first gate electrode structure in the first trench; a body region and the doped region of second conductivity type in the epitaxial layer, the body region is spaced apart from the first gate dielectric layer of the first gate electrode structure, the doped region is separated from the body region by the epitaxial layer and is contiguous with the first gate dielectric layer; a first electrode region of first conductivity type in the body region; a third gate structure on a top surface of the epitaxial layer, including a third gate and a third gate dielectric layer, the third gate structure partially overlaps the first gate dielectric layer and partially overlaps the body region; and a second electrode.

Abstract: This disclosure provides systems, methods, and devices for image signal processing that support high dynamic range (HDR) image processing on image frames with temporally-aligned centers to reduce artifacts resulting from fusing image frames with different temporal centers. In some aspects, a method of image processing includes capturing three or more image frames having at least two different exposure lengths. The three or more image frames are processed to obtain two image frames with temporally-aligned centers, and those two image frames are processed in HDR fusion logic to obtain an output HDR image frame. Other aspects and features are also claimed and described.

Abstract: This disclosure provides systems, methods, and devices for image signal processing that support image signal processing of exposure bracketed image frames. In a first aspect, a method of image processing includes receiving, by at least one processor, image data comprising first image data of a first exposure duration, second image data of a second exposure duration, and third image data of a third exposure duration, wherein the first exposure duration is equal to the third exposure duration; determining, by the at least one processor, fourth image data by subtracting corresponding pixel intensity values of the third image data from the second image data; and determining, by the at least one processor, a first output image frame by combining the fourth image data with the first image data. Other aspects and features are also claimed and described.