Patents by Inventor Fu Chen

Fu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12157952
    Abstract: A method of controlling chemical concentration in electrolyte includes measuring the chemical concentration in the electrolyte in a tank, wherein an end of an exhaust pipe is connected to a top of the tank; determining, by a valve moved along a top surface of the tank, a vapor flux through the exhaust pipe based on the measured chemical concentration; rotating, by using a motor connected to a ball screw connected to the valve, the ball screw to move a gate of the valve based on the determined vapor flux; electroplating, using the electrolyte provided by the tank, wafers respectively in a plurality of electroplating cells that are connected to the tank; and recycling the electrolyte to the tank.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chang Huang, You-Fu Chen, Yu-Chi Tsai, Chu-Ting Chang
  • Patent number: 12160269
    Abstract: A bi-directional and multi-channel optical module incudes an encapsulation casing, a TOSA, a plurality of ROSAs and a plurality of optical folding elements. The TOSA is accommodated in the encapsulation casing. The TOSA includes a light emitting element and a thin film LiNbOx modulator, and a light receiving end of the thin film LiNbOx modulator is optically coupled with the light emitting element. The ROSAs are accommodated in the encapsulation casing. The ROSAs are configured to receive external optical signals propagating into the encapsulation casing. The optical folding elements are optically coupled with a plurality of light propagation ends of the thin film LiNbOx modulator, respectively, for changing a traveling direction of light emitted by the TOSA. Each of the optical folding elements is configured to enable one of the ROSAs share a fiber access terminal with the TOSA.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: December 3, 2024
    Assignee: Global Technology Inc.
    Inventors: Jian-Hong Luo, Dong-Biao Jiang, Fu Chen, Hao Zhou
  • Patent number: 12159931
    Abstract: A nitride-based semiconductor device including a first and a second nitride-based semiconductor layers, a source electrode and a drain electrode, and a gate structure. The gate structure includes at least one conductive layer and two or more doped nitride-based semiconductor layers. The at least one conductive layer includes metal, and is in contact with the second nitride-based semiconductor layer to form a metal-semiconductor junction therebetween. The two or more doped nitride-based semiconductor layers are in contact with the second nitride-based semiconductor layer and abut against the conductive layer, so as to form contact interfaces abutting against the metal-semiconductor junction with the second nitride-based semiconductor.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: December 3, 2024
    Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
    Inventors: Qingyuan He, Ronghui Hao, Fu Chen, Jinhan Zhang, King Yuen Wong
  • Publication number: 20240391488
    Abstract: Systems and methods for determining metrics for construction zone detection and evaluating the performance of construction zone detection. A construction zone can be manually labeled, and the human labels are converted to a format that can be input to a neural network. The neural network input represents polygons indicating the construction zone, as well as various construction zone objects. When an AV drives to the construction zone, the AV detects the construction zone objects and generates a predicted construction zone, including, for example, predicted edges. The predicted connectivity of the construction zone objects is evaluated to determine accuracy of the detected construction zone.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 28, 2024
    Applicant: GM Cruise Holdings LLC
    Inventors: Fu-Chen Yeh, Changkai Zhou, Elad Plaut, Shuqin Xie
  • Publication number: 20240395897
    Abstract: A method of manufacturing a semiconductor device includes forming a conductive layer over a first substrate, forming at least one circuit element at least partially from a semiconductor material of a second substrate, bonding the first substrate to the second substrate, etching a through via extending through the second substrate to partially expose the conductive layer, depositing at least one conductive material in the through via to form a conductive through via electrically coupled to the conductive layer and over the second substrate to form a first contact structure electrically coupling the conductive through via to the at least one circuit element. The at least one circuit element includes at least one of a Schottky diode, a capacitor, or a resistor.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Chia-Ming HUNG, I-Hsuan CHIU, Hsiang-Fu CHEN, Kang-Yi LIEN, Chu-Heng CHEN
  • Publication number: 20240396540
    Abstract: An inverter-based comparator includes an output stage circuit including a P-type output transistor and an N-type output transistor; a first inverter having a first transition voltage with an input node coupled to an input voltage and an output node generating a first inverted voltage and coupled to a gate of the N-type output transistor; and a second inverter having a second transition voltage with an input node coupled to the input voltage and an output node generating a second inverted voltage and coupled to a gate of the P-type output transistor. The first inverter and the second inverter each includes an inverter that includes a first inverter branch composed of at least one first P-type transistor and at least one first N-type transistor; and a second inverter branch composed of at least one second P-type transistor, at least one second N-type transistor and at least two tuning switches.
    Type: Application
    Filed: August 7, 2024
    Publication date: November 28, 2024
    Inventors: Philex Ming-Yan Fan, Yi-Fu Chen, Bo-Rui Chen
  • Patent number: 12153069
    Abstract: The present invention provides a battery probing module, for testing a battery defined with a contact surface having a first electrode area and a second electrode area with different polarities. The battery probing module comprises a frame and a plurality of probe units. The frame has a top plate and a bottom plate opposite to the top plate. Each of the plurality of probe units comprises a base, a first probe, and a plurality of second probes. The base is defined with a top surface and a bottom surface deflectably fixed to the top surface by a fixing unit. The first probe and the plurality of second probes protrude from the bottom surface for contacting the first electrode area and the second electrode area respectively. Wherein the first probe is within a periphery surrounded by the plurality of second probes in a vertical direction of the bottom surface.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: November 26, 2024
    Assignee: Chroma ATE Inc.
    Inventors: Shih-Ching Tan, Chun-Nan Ou, Tzu-Fu Chen, Chen-Chou Wen, Chiang-Cheng Fan
  • Patent number: 12154813
    Abstract: The present disclosure describes an apparatus. The apparatus includes a chuck for placing an object thereon, a gas passage extending along a periphery of an outer sidewall of the chuck and separating the chuck into an inner portion and a sidewall portion, and a plurality of gas holes through the sidewall portion and configured to connect a gas external to the chuck to the gas passage.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ian Hsieh, Che-fu Chen, Yan-Hong Liu
  • Patent number: 12153868
    Abstract: An integrated circuit includes a plurality of metal lines extending along a first direction, the plurality of metal lines being separated, in a second direction perpendicular to the first direction, by integral multiples of a nominal minimum pitch. The integrated circuit further includes a plurality of standard cells, at least one of the plurality of standard cells having a cell height along the second direction being a non-integral multiple of the nominal minimum pitch.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Chun-Fu Chen, Ting-Wei Chiang, Hui-Zhong Zhuang, Hsiang-Jen Tseng
  • Publication number: 20240389340
    Abstract: A ferroelectric tunnel junction is formed, comprising a plurality of layers including at least a bottom electrode layer, a top electrode layer, and at least one ferroelectric layer disposed between the bottom electrode layer and the top electrode layer. The at least one ferroelectric layer comprises a ferroelectric material. At least one layer of the plurality of layers is in contact with the ferroelectric layer and has a coefficient of thermal expansion that is at least 25% lower than a coefficient of thermal expansion of the ferroelectric layer; and inducing ferroelectric phase crystallization in the ferroelectric layer by annealing the plurality of layers.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 21, 2024
    Inventors: Wan-Chen Chen, Tzu-Yu Chen, Chu-Jie Huang, Fu-Chen Chang, Kuo-Chi Tu, Sheng-Hung Shih
  • Publication number: 20240389350
    Abstract: The present disclosure relates to a ferroelectric memory device that includes a bottom electrode, a ferroelectric structure overlying the bottom electrode, and a top electrode overlying the ferroelectric structure where the bottom electrode includes molybdenum.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Harry-Hak-Lay Chuang, Fu-Chen Chang, Tzu-Yu Chen, Sheng-Hung Shih, Kuo-Chi Tu
  • Publication number: 20240387228
    Abstract: The present disclosure describes an apparatus. The apparatus includes a chuck for placing an object thereon, a gas passage extending along a periphery of an outer sidewall of the chuck and separating the chuck into an inner portion and a sidewall portion, and a plurality of gas holes through the sidewall portion and configured to connect a gas external to the chuck to the gas passage.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ian HSIEH, Che-fu CHEN, Yan-Hong LIU
  • Publication number: 20240387300
    Abstract: A manufacturing method of group III-V semiconductor package is provided. The manufacturing method includes the following steps. A wafer comprising group III-V semiconductor dies therein is provided. A chip probing (CP) process is performed to the wafer to determine reliabilities of the group III-V semiconductor dies, wherein the CP process comprises performing a multi-step breakdown voltage testing process to the group III-V semiconductor dies to obtain a first portion of dies of the group III-V semiconductor dies with breakdown voltages to be smaller than a predetermined breakdown voltage. A singulation process is performed to separate the group III-V semiconductor dies from the wafer. A package process is performed to form group III-V semiconductor packages including the group III-V semiconductor dies. A final testing process is performed on the group III-V semiconductor packages.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-An Lai, Chan-Hong Chern, Chih-Hua Wang, Chu-Fu Chen, Kun-Lung Chen
  • Publication number: 20240383005
    Abstract: A semiconductor device and method of manufacturing the device that includes a capacitive micromachined ultrasonic transducer (CMUT). The CMUT includes an integrated circuit substrate, and a sensing electrode positioned on the integrated substrate. The sensing electrode includes a sidewall that forms a wall of an isolation trench adjacent to the sensing electrode, and is patterned before covering dielectric layers are deposited. After patterning of the sensing electrode, one or more dielectric layers are patterned, with one dielectric layer patterned on the sensing electrode and sidewall, and which has a thickness corresponding to the surface roughness of the sensing electrode. The CMUT further includes a membrane positioned above the sensing electrode forming a cavity therein.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Wei-Tung Huang, Hsiang-Fu Chen
  • Publication number: 20240375943
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Wen-Chuan Tai, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu, Fan Hu
  • Publication number: 20240373645
    Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Fu-Chen Chang, Chih-Hsiang Chang, Sheng-Hung Shih
  • Publication number: 20240371980
    Abstract: A method for making a semiconductor device includes: forming a first gate stack over a first fin; forming a first gate spacer extending along a side of the first gate stack; forming a second gate spacer over the first gate spacer; forming a third gate spacer over the second gate spacer, the third gate spacer; forming a source/drain region adjacent the third gate spacer; depositing an interlayer dielectric (ILD) over the source/drain region, the ILD including a third dielectric material; and removing at least a portion of the second gate spacer to form a void, while exposing a top surface of the ILD. The void includes a vertical portion extending between the first gate spacer and the source/drain region, and between the first gate spacer and the ILD. The void includes a horizontal portion extending beneath the source/drain region.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu Ming Hsiao, Ming-Jhe Sie, Hsiu-Hao Tsao, Hong Pin Lin, Che-fu Chen, An Chyi Wei, Yi-Jen Chen
  • Publication number: 20240371643
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes an insulating layer over the substrate. The semiconductor device structure includes a first gate structure and a second gate structure embedded in the insulating layer. The first gate structure is wider than the second gate structure, the first gate structure includes a first gate dielectric layer and a first gate electrode layer over the first gate dielectric layer, the second gate structure includes a second gate dielectric layer and a second gate electrode layer over the second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer are made of a same material, and the second gate dielectric layer is thinner than the first gate dielectric layer.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Lun LIN, Yen-Fu CHEN, Da-Yuan LEE, Tsung-Da LIN, Chi On CHUI
  • Publication number: 20240362485
    Abstract: Systems and methods for detecting cracks in a surface by analyzing a video, including a full-HD video, of the surface. The video contains successive frames, wherein individual frames of overlapping consecutive pairs of the successive frames have overlapping areas and a crack that appears in a first individual frame of a consecutive pair of the successive frames also appears in at least a second individual frame of the consecutive pair. A fully convolutional network (FCN) architecture implemented on a processing device is then used to analyze at least some of the individual frames of the video to generate crack score maps for the individual frames, and a parametric data fusion scheme implemented on a processing device is used to fuse crack scores of the crack score maps of the individual frames to identify cracks in the individual frames.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Fu-Chen Chen, Mohammad R. Jahanshahi
  • Patent number: D1051456
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: November 12, 2024
    Assignee: STARFORCE INCORPORATED
    Inventor: Dung-Fu Chen