Abstract: Systems and methods are disclosed for fabricating a semiconductor light-emitting diode (LED) device by forming an n-doped gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device.

Abstract: Systems and methods are disclosed for fabricating a semiconductor light-emitting diode (LED) device by forming an n-doped gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device.

Abstract: A surface-mounted over-current protection device with positive temperature coefficient (PTC) behavior is disclosed. The surface-mounted over-current protection device comprises a first metal foil, a second metal foil corresponding to the first metal foil, a PTC material layer stacked between the first metal foil and the second metal foil, a first metal electrode, a first metal conductor electrically connecting the first metal foil to the first metal electrode, a second metal electrode corresponding to the first metal electrode, a second metal conductor electrically connecting the second metal foil to the second metal electrode, and at least one insulated layer to electrically insulate the first metal electrode from the second metal electrode. The surface-mounted over-current protection device, at 25° C., indicates that a hold current thereof divided by the product of a covered area thereof and the number of the conductive composite module is at least 0.16 A/mm2.

Abstract: A chemical mechanical polishing device used to polish a wafer according to the present invention includes a polishing table, a polishing pad, a slurry supply device, a wafer carrier and a high-pressure liquid cleaning device. The polishing pad is disposed on the polishing table to polish the wafer. The slurry supply device is disposed on the polishing table to supply the slurry. In addition, the wafer carrier is disposed the polishing table to carry the wafer in such a manner that the wafer is brought into contact with the polishing pad. Besides, the high-pressure cleaning device is disposed on the polishing table to remove the impurities on the polishing pad by high-pressure liquid.

Abstract: An over-current protection device comprises a chemically cross-linked positive temperature coefficient (PTC) layer and two electrode foils that can be connected to a power source to allow current to flow through the chemically cross-linked polymeric PTC layer. The chemically cross-linked polymeric PTC layer comprises at least two different PTC polymer layers, and each polymer layer comprises polymer and conductive filler and has a volumetric resistivity between 10?1 and 10?3 ?-cm. The polymer layers have different functional groups and are alternately stacked and hot pressed to generate chemical cross-linking therebetween so as to form the chemically cross-linked polymeric PTC layer, wherein the potential difference of every 0.1 mm in thickness of the chemically cross-linked polymeric PTC layer is less than 30 volts.

Abstract: An over-current protection device comprises two metal foils and a positive temperature coefficient (PTC) material layer. The PTC material layer is sandwiched between the two metal foils and comprises plural crystalline polymers with at least one polymer melting point below 115° C., and a non-oxide electrically conductive ceramic powder. The non-oxide electrically conductive ceramic powder exhibits a certain particle size distribution. The PTC material layer has a resistivity below 0.1 ?-cm. The initial resistance of the device is below 20 m?, and the area of the PTC material layer is below 30 mm2. The over-current protection device exhibits a surface temperature below 100° C. under the trip state of over-current protection.

Abstract: The present invention discloses an over-current protection device comprising two metal foils and a positive temperature coefficient (PTC) material layer. The PTC material layer is sandwiched between the two metal foils and contains at least one crystalline polymer, a non-oxide electrically conductive ceramic powder and a non-conductive filler. The non-oxide electrically conductive ceramic powder exhibits a certain particle size distribution. The PTC material layer presents resistivity below 0.1 ?-cm.

Abstract: The present invention is to provide a high voltage over-current protection device and a manufacturing method thereof, in which PTC polymers are cross-linked by chemical cross-linking. With the method of the present invention, the high voltage endurance of the PTC devices is enhanced. In addition, the internal stress and degradation of polymers caused by irradiation treatment are prevented.

Abstract: The present invention relates to a method for machining a wafer, comprising: (a) providing a wafer having an active surface and a backside surface; (b) attaching a plate substrate to the active surface of the wafer; (c) grinding the backside surface of the wafer; (d) removing the plate substrate; and (e) sawing the wafer. Therefore, warping of the thin wafer can be avoided.

Abstract: An over-current protection device comprises two electrode foils, at least one conductive layer and a positive temperature coefficient (PTC) layer, wherein at least one of the electrode foils comprises a micro-rough surface, and the micro-rough surface of the electrode foil is overlaid by the conductive layer. The PTC layer is stacked between the two electrode foils, and at least one of the surfaces of the PTC layer is physically in contact with the at least one conductive layer. Accordingly, the conductive layer located between the PTC layer and the electrode foil can effectively decrease the contact resistance therebetween and avoid arcing.

Abstract: A device for upgrading a firmware of a display apparatus is provided. The device comprises a USB port, a USB control chip and a micro-controller. The USB port is adapted for connecting with a storage device providing upgrading data. The USB control chip is coupled to the USB port for controlling the transmission of the upgrading data from the storage device to at least one component of the display apparatus to be upgraded. The micro-controller is coupled to the USB chip and is adapted for reading the upgrading data from the storage device and allocating the upgrading data to the components.

Abstract: A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

Abstract: A bipolar transistor, with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and over the collector region beside and spaced from the emitter structure. A dielectric layer is deposited over the substrate and connections are formed to the extrinsic base structure, the emitter structure and the collector region.

Abstract: A method of manufacturing a BiCMOS integrated circuit including a CMOS transistor having a gate structure, and a heterojunction bipolar transistor having an extrinsic base structure. A substrate is provided, and a polysilicon layer is formed over the substrate. The gate structure and the extrinsic base structure are formed in the polysilicon layer. A plurality of contacts is formed through the interlevel dielectric layer to the CMOS transistor and the heterojunction bipolar transistor.

Abstract: An over-current protection device comprises two electrode foils, at least one conductive layer and a positive temperature coefficient (PTC) layer, wherein at least one of the electrode foils comprises a micro-rough surface, and the micro-rough surface of the electrode foil is overlaid by the conductive layer. The PTC layer is stacked between the two electrode foils, and at least one of the surfaces of the PTC layer is physically in contact with the at least one conductive layer. Accordingly, the conductive layer located between the PTC layer and the electrode foil can effectively decrease the contact resistance therebetween and avoid arcing.

Abstract: In various embodiments, methods and compositions are provided comprising titanium dioxide and silica spacers having improved light stability for use in paper, plastic and paints.

Abstract: A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.

Abstract: A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.

Abstract: A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

Abstract: A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.