Patents by Inventor Fu Chu

Fu Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6139251
    Abstract: A stepper alignment method and apparatus for transferring circuit layout on a mask to a wafer precisely includes a stepper located in a susceptor and includes a vacuum chuck and a movable vacuum chuck. The wafer has two notches on its perimeter. The vacuum chuck has two sets of photo sensors mating against the notches and a central circular opening for housing the movable vacuum chuck therein. The movable vacuum chuck holds the wafer by means of vacuum force and is able to rotate and move linearly to align the notches of the wafer against the photo sensors accurately at high speed.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: October 31, 2000
    Assignee: Nanya Technology Corporation
    Inventor: Ron-Fu Chu
  • Patent number: 5960062
    Abstract: A method of recording the bi-directional communication between a customer premises equipment (CPE) and a server of a stored program controlled system (SPCS) in an analog display services interface (ADSI) for facilitating the troubleshooting therein is disclosed. The present invention includes accessing the telephone set by a user, therefore initiating the communication between the telephone set and the server. After receiving an alerting signal from the server, the alerting signal and the corresponding received time of the alerting signal are recorded into a trace area in the telephone set. A first acknowledgment signal is sent to the server after the alerting signal is recognized, and the first acknowledgment signal is then recorded in the trace area. At least one message is sent from the server, and then the message, a start received time and an end received time of the message are recorded into the trace area and a message buffer.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: September 28, 1999
    Assignee: Inventec Corporation
    Inventors: Jackson Chang, Jeffrey Lai, Henry Lin, Men-Fu Chu
  • Patent number: 5954542
    Abstract: A rear shielding shell for a USB plug connector is disclosed. The rear shielding shell defines a main body for connection with a front shielding shell, and a guiding sleeve for an extension of a cable therethrough to connect with contacts mounted to a dielectric body. The guiding sleeve is formed with a retaining portion by applying a cutting operation to the guiding sleeve. The retaining portion can be extended onto the cable extending through the sleeve and fixedly engage therewith and reduce a gap between the cable and the sleeve.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: September 21, 1999
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventors: Kun-Tsan Wu, Fu-Chu Wang
  • Patent number: 5863307
    Abstract: A Chemical-Mechanical Polish (CMP) planarizing method and a Chemical-Mechanical Polish (CMP) slurry composition for Chemical-Mechanical Polish (CMP) planarizing of copper metal and copper metal alloy layers within integrated circuits. There is first provided a semiconductor substrate having formed upon its surface a patterned substrate layer. Formed within and upon the patterned substrate layer is a blanket copper metal layer or a blanket copper metal alloy layer. The blanket copper metal layer or blanket copper metal alloy layer is then planarized through a Chemical-Mechanical Polish (CMP) planarizing method employing a Chemical-Mechanical Polish (CMP) slurry composition. The Chemical-Mechanical Polish (CMP) slurry composition comprises a non-aqueous coordinating solvent and a halogen radical producing specie.
    Type: Grant
    Filed: May 18, 1998
    Date of Patent: January 26, 1999
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Mei Sheng Zhou, Ron-Fu Chu
  • Patent number: 5857127
    Abstract: An apparatus for use in the photoresist development process of an integrated circuit fabrication is provided to improve the uniformity of development. The apparatus includes: a holder which includes a vertical spindle and a chuck fixed on the top of the vertical spindle, for horizontally holding a semiconductor wafer; a liquid feeder disposed above the holder, for supplying a developer onto the semiconductor wafer; a cup-type housing disposed under the holder, wherein the bottom of the cup-type housing includes a valve for draining the developer and a hole for allowing the vertical spindle to penetrate through; and a hoisting instrument fixed on the bottom of the cup-type housing, so that when the cup-type housing is lifted, the edge of the semiconductor wafer tightly contacts the sidewall of the cup-type housing, thereby forming a dish-like container for containing the developer.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: January 5, 1999
    Assignee: Nan Ya Technology Corp.
    Inventor: Ron-Fu Chu
  • Patent number: 5795699
    Abstract: A method for forming upon a reflective layer, such as a reflective conducting layer, within an integrated circuit an Anti-Reflective Coating (ARC) which simultaneously possesses adhesion promotion characteristics for an organic layer to be formed upon the reflective layer. There is first formed upon a semiconductor wafer a reflective integrated circuit layer which may be a hydrophilic reflective integrated circuit layer or a hydrophobic integrated circuit layer. The semiconductor wafer is then immersed into and withdrawn from a Langmuir trough having formed therein a Langmuir-Blodgett (LB) monolayer film of a dye surfactant molecule ordered upon a surface of water. Upon withdrawing the wafer from the Langmuir trough, there is formed upon the reflective integrated circuit layer an ordered LB film of the dye surfactant molecule. The chromophore groups within the dye surfactant molecule and ordered LB film provide ARC characteristics to the reflective layer.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: August 18, 1998
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Mei Sheng Zhou, Ron-Fu Chu
  • Patent number: 5746819
    Abstract: The present invention discloses high solids slurries of sulfate process, anatase titanium dioxide pigment. The improvements of these slurries over those of the prior art are improved slurry stability, tolerance to calcium and magnesium ions, foaming tendencies and reduced tendency to flocculate. The slurries of the present invention are comprised of at least 65% by weight of anatase TiO.sub.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: May 5, 1998
    Assignee: SCM Chemicals, Inc.
    Inventors: Robert J. Kostelnik, Fu-Chu Wen
  • Patent number: 5734594
    Abstract: This computer system, as well as its method of operation, corrects the position data used to define the location of alignment marks on a workpiece. The first step is to scan marks along a first direction to determine the direction of wafer scaling along the first direction. Second, scan marks along a second direction to determine the direction of wafer scaling along the second direction. Next, scan a first set of alignment marks on a workpiece oriented in a first direction and a second set of alignment marks on the workpiece oriented in a second direction in an initial sequence to collect initial direction data on the location. Then, scan the first set of alignment marks and the second set of alignment marks in a reverse sequence to collect reverse direction data on the location. Finally, average the initial direction data and the reverse direction data. This enables correction of false alignment data attributable to falsely measured locations of alignment marks.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: March 31, 1998
    Assignee: Chartered Semiconductor Manufacturing Pte Ltd.
    Inventors: Ron-Fu Chu, Zadig Cheung-Ching Lam
  • Patent number: 5728493
    Abstract: An antireflection mask and method of using the antireflection mask to form contact holes for an integrated circuit wafer are described. The antireflection mask has a patterned opaque layer formed on a transparent mask substrate. The patterned opaque layer has first openings for exposing photoresist in regions where the photoresist is thicker and second openings for exposing photoresist in regions where the photoresist is thinner. A patterned layer of antireflection material having a light transmittance of less than 100% is formed over the second openings but not over the first openings. Light is passed through the mask to expose a layer of photoresist. The light exposing the thinner photoresist regions is attenuated by the antireflection material thereby compensating for variations in photoresist thickness. In addition the antireflection material reduces reflections from the patterned opaque layer of the mask.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: March 17, 1998
    Assignee: Chartered Semiconductor Manufacturing PTE LTD
    Inventors: Chet Ping Lim, Ron-Fu Chu
  • Patent number: 5582679
    Abstract: A method for dry etching metal films, specifically aluminum, is described. This process uses photoresist as a mask with a gas mixture of BCl3, Cl2 and N2 used for the RIE. The addition of specific amounts of N2 to the etching chemistry results in non-tapered or non-undercut aluminum shapes. These desired shapes are attributed to the creation of polymer on the sidewall of the aluminum during the etching procedure, thus protecting against the isotropic components of RIE process, which cause the tapering. This RIE process can also be conducted at high enough temperatures, needed to avoid deleterious microloading effects.
    Type: Grant
    Filed: September 12, 1994
    Date of Patent: December 10, 1996
    Assignee: Chartered Semiconductor Manufacturing Pte Ltd.
    Inventors: Liu Lianjun, Ron-Fu Chu
  • Patent number: 5496666
    Abstract: This invention provides an improved process latitude mask for forming contact or via hole openings in a photoresist masking layer in the fabrication of semiconductor integrated circuits. The invention also provides a method of forming contact or via hole openings in a photoresist masking layer using an improved process latitude mask. The improved process latitude mask, called a dot mask, uses an opaque blocking area formed in the center of the primary opening in a projection mask for forming contact or via hole openings in a photoresist layer. The opaque blocking area is equal to or less than the area of the primary opening divided by nine. The opaque blocking area is small enough so that it will not form an image in the photoresist layer. The opaque blocking area modifies the light intensity profile at the photoresist layer in a manner which improves process latitude.
    Type: Grant
    Filed: October 27, 1994
    Date of Patent: March 5, 1996
    Assignee: Chartered Semiconductor Manufacturing PTE Ltd.
    Inventors: Ron-Fu Chu, Chun H. Yik
  • Patent number: 5440022
    Abstract: A novel human hepatokine, referred to hereinafter as HPX, has been isolated and purified from human fetal hepatocytes. HPX has a molecular weight of approximately 15 kD, a pI of about 6, and has been found to promote hepatocyte growth activity in vitro and in vivo.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: August 8, 1995
    Assignee: Panorama Research, Inc.
    Inventors: Chu-tse Wu, Qiang Tu, Fu-chu He, James W. Larrick
  • Patent number: 4441682
    Abstract: A rear-view-mirror locking mechanism for a car comprises a longitudinal arm for holding the mirror and a U-shaped supporting bar coupled with said longitudinal arm through a locking screw and two spacing plates thereof. By turning the screw to abut tightly against the surface of the longitudinal arm, the supporting bar and the longitudinal arm are locked in a fixed position, secured at the fender of the car thus holding the mirror firmly.
    Type: Grant
    Filed: July 27, 1981
    Date of Patent: April 10, 1984
    Inventor: Fu-Chu Su
  • Patent number: 4385975
    Abstract: A method of forming a wide deep dielectric filled isolation trench in the surface of a silicon semiconductor substrate by forming a wide plug of chemical vapor deposited silicon dioxide in the trench, filling the remaining unfilled trench portions by chemical vapor depositing a layer of silicon dioxide over the substrate and etching back this layer. The method produces chemically pure, planar wide deep dielectric filled isolation trenches and may also be used to simultaneously produce narrow deep dielectric filled isolation trenches.
    Type: Grant
    Filed: December 30, 1981
    Date of Patent: May 31, 1983
    Assignee: International Business Machines Corp.
    Inventors: Shao-Fu Chu, Allen P. Ho, Cheng T. Horng, Bernard M. Kemlage
  • Patent number: D409778
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: May 11, 1999
    Assignee: Kung Long Batteries Industrial Co. Ltd.
    Inventor: Sung-Fu Chu