Abstract: Among other things, one or more systems and techniques for removing a photoresist from a semiconductor wafer are provided. The photoresist is formed over the semiconductor wafer for patterning or material deposition. Once completed, the photoresist is removed in a manner that mitigates damage to the semiconductor wafer or structures formed thereon. In an embodiment, trioxygen liquid is supplied to the photoresist. The trioxygen liquid is activated using an activator, such as an ultraviolet activator or a hydrogen peroxide activator, to create activated trioxygen liquid used to remove the photoresist. In an embodiment, the activation of the trioxygen liquid results in free radicals that aid in removing the photoresist. In an embodiment, an initial photoresist strip, such as using a sulfuric acid hydrogen peroxide mixture, is performed to remove a first portion of the photoresist, and the activated trioxygen liquid is used to remove a second portion of the photoresist.

Abstract: The embodiment of the present invention provides a method for a 3-D projection printing system and a system thereof, more particularly to a system adopts both ways of look-up table and interpolation method to calibrate. The embodiment of the present invention provides a portable calibration fixture system and a flexible 3-D projection printing system in order to improve calibration precision, facilitate calibration and printing operations, increase printing effect and save cost.

Abstract: A method for an improved 3-D printing system and a system thereof is disclosed. The method is able to blur and sharpen pattern images, and the system is flexible in assembly in order to benefit the convenience of printing, the speed of printing, and the cost of hardware and manufacturing.

Abstract: An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.

Abstract: A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.

Abstract: Among other things, one or more systems and techniques for removing a photoresist from a semiconductor wafer are provided. The photoresist is formed over the semiconductor wafer for patterning or material deposition. Once completed, the photoresist is removed in a manner that mitigates damage to the semiconductor wafer or structures formed thereon. In an embodiment, trioxygen liquid is supplied to the photoresist. The trioxygen liquid is activated using an activator, such as an ultraviolet activator or a hydrogen peroxide activator, to create activated trioxygen liquid used to remove the photoresist. In an embodiment, the activation of the trioxygen liquid results in free radicals that aid in removing the photoresist. In an embodiment, an initial photoresist strip, such as using a sulfuric acid hydrogen peroxide mixture, is performed to remove a first portion of the photoresist, and the activated trioxygen liquid is used to remove a second portion of the photoresist.

Abstract: The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer.

Abstract: A memory device includes: a substrate; a channel layer on the substrate, in which the channel layer includes a T-shape having a horizontal portion with a first end and a second end and a vertical portion having a third end; a gate structure on a side of the vertical portion; an oxide-nitride-oxide (ONO) layer between the gate structure and the vertical portion; a source region on the first end of the horizontal portion; and a drain region on the third end of the vertical portion.

Abstract: The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.

Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

Abstract: A light sensor for sensing an illumination of a partial area is disclosed. The light sensor includes a first case, a second case, a first light absorption layer and at least one sensing module. The first case includes at least one hole. The at least one hole includes an axis. The second case is fastened to the first case, and a containing space is formed between the first case and the second case. The first light absorption layer is located on the first case. The at least one sensing module is located in the containing space, and the position of the at least one sensing module is located on the axis of the hole. The at least one sensing module is used for sensing the light from the partial area which passes through the hole so as to obtain the illumination of the partial area.

Abstract: The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.

Abstract: Embodiments of the present invention provide methods for optimizing a lithographic projection apparatus including optimizing projection optics therein. The current embodiments include several flows including optimizing a source, a mask, and the projection optics and various sequential and iterative optimization steps combining any of the projection optics, mask and source. The projection optics is sometimes broadly referred to as “lens”, and therefore the optimization process may be termed source mask lens optimization (SMLO). SMLO may be desirable over existing source mask optimization process (SMO) or other optimization processes that do not include projection optics optimization, partially because including the projection optics in the optimization may lead to a larger process window by introducing a plurality of adjustable characteristics of the projection optics.

Abstract: A drying apparatus includes a gas flow channel, a first hollow fiber module, a second hollow fiber module, a gas driver and a control unit. The gas flow channel is used to accommodate an article and has a first terminal and a second terminal. The first and second hollow fiber modules are disposed at the first and second terminals respectively to adsorb water or to be electrified to desorb water. The gas driver disposed in a gas flow path of the gas flow channel drives the gas flowing into the gas flow channel through the first hollow fiber module and flowing out from the gas flow channel through the second hollow fiber module, or flowing into the gas flow channel through the second hollow fiber module and flowing out from the gas flow channel through the first hollow fiber module. The control unit provides power to the first and second hollow fiber modules and controls the gas driver.

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

Abstract: The disclosure discloses a housing manufacturing method including: providing a first fiberglass plate; coating a first glue on the first fiberglass plate; providing a second fiberglass plate; covering the second fiberglass plate onto the first glue; and curing the first glue to become a cushion adhesive layer, in which the first fiberglass plate, the cushion adhesive layer, and the second fiberglass plate constitute a composite board. The disclosure further discloses a housing manufactured by the foregoing composite plate manufacturing method.

Abstract: A signal transceiving circuit comprising an IC including a signal transmitting part. The signal transmitting part comprises: a first I/O pad; a second I/O pad; a first output stage circuit, coupled to the first I/O pad; a second output stage circuit, coupled to the second I/O pad; and a first surge protecting device, comprising a first terminal coupled to the first output stage circuit and the first I/O pad, and comprising a second terminal coupled to the second output stage circuit and the second I/O pad.

Abstract: A video decoding apparatus capable of controlling presentation of sub-pictures includes a first decoder, a second decoder, a first scaler, a second scaler and a combiner. The first decoder and the second decoder respectively decode a digital audio/video signal to generate a decoded video and a decoded sub-picture. In accordance with an output picture size, the decoded video size, the decoded sub-picture size and a sub-picture aspect ratio, the first scaler and the second scaler generate a first scaling factor and a second scaling factor. The combiner combines the decoded video and the decoded sub-picture according to the first scaling factor and the second scaling factor and outputs the combination thereof. A video decoding method and a digital audio/video playback system capable of controlling presentation of sub-pictures are also disclosed.