Patents by Inventor Fu Tang

Fu Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220060116
    Abstract: A power path switch circuit includes: a power transistor unit including: a first vertical double-diffused metal oxide semiconductor (VDMOS) device, wherein a first current outflow end of the first VDMOS device is coupled to an output end of a power path; and a second VDMOS device, wherein a first current inflow end of the first VDMOS device and a second current inflow end of the second VDMOS device are coupled with a supply end of the power path; and a voltage locking circuit coupled to the first current outflow end and the second current outflow end, for locking a voltage at the second current outflow end to a voltage at the first current outflow end, so that there is a predetermined ratio between a first conductive current flowing through the first VDMOS device and a second conductive current flowing through the second VDMOS device.
    Type: Application
    Filed: July 5, 2021
    Publication date: February 24, 2022
    Inventors: Hsin-Yi Wu, Chien-Fu Tang
  • Patent number: 11205644
    Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: December 21, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Rui Wu, Fu-Tang Huang, Chia-Cheng Chen, Chun-Hsien Lin, Hsuan-Hao Mi, Yu-Cheng Pai
  • Patent number: 11189518
    Abstract: A method of processing a semiconductor wafer is provided. The method includes providing a semiconductor wafer having a front side and a back side, the semiconductor wafer provided with a circuit layer at the front side and a patterned surface at the back side, forming a sacrificial layer on the back side, mounting a tape on the sacrificial layer, the sacrificial layer isolating the patterned surface from the tape, wherein adhesion strength between the sacrificial layer and the patterned surface is larger than that between the sacrificial layer and the tape, dicing the semiconductor wafer at the back side through the tape, defining individual chips on the semiconductor wafer, and expanding the tape to separate the chips from each other.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 30, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yan Ting Shen, Bo Hua Chen, Fu Tang Chu, Wen Han Yang
  • Publication number: 20210350738
    Abstract: A shift register unit and a driving method thereof, a scan driving circuit, an array substrate and a display device. The shift register unit includes: an input circuit configured for setting the first node to a valid level in a case where the input terminal is at a valid level; a first reset control circuit configured for setting the second node to a valid level and setting the input terminal to an invalid level in a case where the reset terminal is at a valid level; an output circuit configured for setting the output terminal to a valid level by using a clock signal in a case where the first node is at the valid level; a reset circuit configured for setting the first node and the output terminal to an invalid level in a case where the second node is at a valid level.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 11, 2021
    Inventors: Hongtao GUO, Guowei CHAI, Fu TANG, Bangrong XU
  • Patent number: 11169179
    Abstract: A current sensing circuit having self-calibration includes two leads, a sensing element having a sensing resistance, and a sensing and calibration circuit. The sensing and calibration circuit senses and calibrates a sensing voltage of the sensing element, and senses a sensing current through the sensing element according to the sensing resistance and the sensing voltage, to generate a current sensing output signal. The sensing and calibration circuit includes two pads, a V2I circuit, a current mirror circuit and an I2V circuit. The sensing element has a first temperature coefficient (TC). The TC and/or the resistance of an adjusting resistor in the V2I circuit and an adjusting resistor in the I2V circuit are determined according to the first TC, such that the TC of the current sensing output signal is equal to 0.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: November 9, 2021
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Isaac Y. Chen, Chien-Fu Tang, Hsin-Yi Wu, Kai-Chuan Chan, Yu-Lin Yang
  • Publication number: 20210287088
    Abstract: A training method suitable for a reinforcement learning system with a reward function to train a reinforcement learning model and including: defining at least one reward condition of the reward function; determining at least one reward value range corresponding to the at least one reward condition; searching for at least one reward value from the at least one reward value range by a hyperparameter tuning algorithm; and training the reinforcement learning model according to the at least one reward value.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 16, 2021
    Inventors: Yu-Shao PENG, Kai-Fu TANG, Edward CHANG
  • Publication number: 20210287793
    Abstract: A control method includes following operations. A symptom input status and a test result status are collected. A neural network is utilized to generate a test suggestion, a predicted test result distribution and a predicted disease distribution according to the symptom input status and the test result status. The test suggestion includes a candidate test. Information gains of the candidate test relative to diseases are estimated according to the predicted test result distribution and the predicted disease distribution. An explainable description about the test suggestion is generated according to the information gains of the candidate test. Another explainable description about a predicted disease list can be generated according to an attention input.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 16, 2021
    Inventors: Yang-En CHEN, Kai-Fu TANG, Edward CHANG
  • Publication number: 20210270870
    Abstract: A current sensing circuit having self-calibration includes two leads, a sensing element having a sensing resistance, and a sensing and calibration circuit. The sensing and calibration circuit senses and calibrates a sensing voltage of the sensing element, and senses a sensing current through the sensing element according to the sensing resistance and the sensing voltage, to generate a current sensing output signal. The sensing and calibration circuit includes two pads, a V2I circuit, a current mirror circuit and an I2V circuit. The sensing element has a first temperature coefficient (TC). The TC and/or the resistance of an adjusting resistor in the V2I circuit and an adjusting resistor in the I2V circuit are determined according to the first TC, such that the TC of the current sensing output signal is equal to 0.
    Type: Application
    Filed: December 8, 2020
    Publication date: September 2, 2021
    Inventors: Isaac Y. Chen, Chien-Fu Tang, Hsin-Yi Wu, Kai-Chuan Chan, Yu-Lin Yang
  • Patent number: 11101370
    Abstract: A method for forming layers suitable for a V-NAND stack is disclosed. Specifically, the method may include multiple cycles for forming an oxide and a nitride in order to form an oxynitride layer.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 24, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Fu Tang, Qi Xie, Jan Willem Maes, Xiaoqiang Jiang, Michael Eugene Givens
  • Publication number: 20210167691
    Abstract: A low delay time power converter circuit includes a driver circuit and a load. The driver circuit generates a switching driving signal to control the load. The driver circuit includes a switching control circuit and an output stage circuit which includes a first power switch, a second power switch and an impedance adjusting circuit. When the switching control circuit controls the switching driving signal to a first voltage level at a first time point, the first power switch is turned ON and then is turned OFF after a predetermined period. When the switching control circuit controls the switching driving signal to a second voltage level at a second time point, the second power switch is turned ON. The time point when the first power switch is turned OFF is earlier than the second time point. A resistance of the impedance adjusting circuit is larger than a conductive resistance of the first power switch.
    Type: Application
    Filed: July 12, 2020
    Publication date: June 3, 2021
    Inventors: Isaac Y. Chen, Chien-Fu Tang, Jo-Yu Wang
  • Publication number: 20210151342
    Abstract: A method of processing a semiconductor wafer is provided. The method includes providing a semiconductor wafer having a front side and a back side, the semiconductor wafer provided with a circuit layer at the front side and a patterned surface at the back side, forming a sacrificial layer on the back side, mounting a tape on the sacrificial layer, the sacrificial layer isolating the patterned surface from the tape, wherein adhesion strength between the sacrificial layer and the patterned surface is larger than that between the sacrificial layer and the tape, dicing the semiconductor wafer at the back side through the tape, defining individual chips on the semiconductor wafer, and expanding the tape to separate the chips from each other.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 20, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yan Ting SHEN, Bo Hua CHEN, Fu Tang CHU, Wen Han YANG
  • Publication number: 20210043324
    Abstract: A computer aided medical method include following steps. An initial symptom is collected through an interaction interface. A representative prediction model is selected from plural candidate prediction models according to the initial symptom. The candidate prediction models are trained by a machine learning algorithm according to clinical data. A series of sequential actions is generated according to the representative prediction model and the initial symptom. The sequential actions are selected from plural candidate actions in the representative prediction model. The candidate actions include plural inquiry actions and plural disease prediction actions. Each of the sequential actions is one of the inquiry actions or the disease prediction actions. The series of sequential actions is displayed on the interaction interface.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: Kai-Fu Tang, Hao-Cheng Kao, Chun-Nan Chou, Edward Chang
  • Publication number: 20210005723
    Abstract: Methods for forming a metal silicate film on a substrate in a reaction chamber by a cyclical deposition process are provided. The methods may include: regulating the temperature of a hydrogen peroxide precursor below a temperature of 70° C. prior to introduction into the reaction chamber, and depositing the metal silicate film on the substrate by performing at least one unit deposition cycle of a cyclical deposition process. Semiconductor device structures including a metal silicate film formed by the methods of the disclosure are also provided.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Fu Tang, Peng-Fu Hsu, Michael Eugene Givens, Qi Xie
  • Patent number: 10872870
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 22, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Patent number: 10854335
    Abstract: A computer aided medical method include following steps. An initial symptom is collected through an interaction interface. A representative prediction model is selected from plural candidate prediction models according to the initial symptom. The candidate prediction models are trained by a machine learning algorithm according to clinical data. A series of sequential actions is generated according to the representative prediction model and the initial symptom. The sequential actions are selected from plural candidate actions in the representative prediction model. The candidate actions include plural inquiry actions and plural disease prediction actions. Each of the sequential actions is one of the inquiry actions or the disease prediction actions. The series of sequential actions is displayed on the interaction interface.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: December 1, 2020
    Assignee: HTC Corporation
    Inventors: Kai-Fu Tang, Hao-Cheng Kao, Chun-Nan Chou, Edward Chang
  • Patent number: 10854444
    Abstract: In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: December 1, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Suvi P. Haukka, Fu Tang, Michael E. Givens, Jan Willem Maes, Qi Xie
  • Publication number: 20200342989
    Abstract: A computer aided medical method includes the following steps. An initial symptom of a patient and context information is collected through an interaction interface. Actions in a series are sequentially generated according to the candidate prediction models and the initial symptom. Each of the actions corresponds to one of the inquiry actions or one of the disease prediction actions. If the latest one of the sequential actions corresponds to one of the disease prediction actions, potential disease predictions are generated in a first ranking evaluated by the candidate prediction models. The first ranking is adjusted into a second ranking according to the context information. A result prediction corresponding to the potential disease predictions is generated in the second ranking.
    Type: Application
    Filed: July 3, 2020
    Publication date: October 29, 2020
    Inventors: Kai-Fu TANG, Edward CHANG, Hao-Cheng KAO
  • Patent number: 10818758
    Abstract: Methods for forming a metal silicate film on a substrate in a reaction chamber by a cyclical deposition process are provided. The methods may include: regulating the temperature of a hydrogen peroxide precursor below a temperature of 70° C. prior to introduction into the reaction chamber, and depositing the metal silicate film on the substrate by performing at least one unit deposition cycle of a cyclical deposition process. Semiconductor device structures including a metal silicate film formed by the methods of the disclosure are also provided.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 27, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Fu Tang, Peng-Fu Hsu, Michael Eugene Givens, Qi Xie
  • Publication number: 20200266054
    Abstract: In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.
    Type: Application
    Filed: January 27, 2020
    Publication date: August 20, 2020
    Inventors: Suvi P. Haukka, Fu Tang, Michael E. Givens, Jan Willem Maes, Qi Xie
  • Publication number: 20200258871
    Abstract: The present disclosure provides a package stack structure and a method for manufacturing the same. The method is characterized by stacking coreless circuit portions on the board of an electronic component to reduce the overall thickness of the package stack structure.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 13, 2020
    Inventors: Han-Hung Chen, Yuan-Hung Hsu, Chang-Fu Lin, Rung-Jeng Lin, Fu-Tang Huang