Patents by Inventor Fu Wang
Fu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12356600Abstract: A static random-access memory (SRAM) cell including a transistor is introduced. The transistor includes substrate and gate stack structure disposed over the substrate, in which the gate stack structure includes a gate oxide layer, a ferroelectric layer, and a conductive layer. The gate oxide layer is disposed over the substrate; the ferroelectric layer is disposed over the gate oxide layer, wherein the ferroelectric layer has a negative capacitance effect; and the first conductive layer, disposed over the ferroelectric layer. A method of adjusting a threshold voltage of a transistor in the SRAM is also introduced.Type: GrantFiled: March 24, 2022Date of Patent: July 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
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Patent number: 12347486Abstract: A forming method of a ReRAM array includes steps as follows: Firstly, a first pulse is applied to a first ReRAM unit in the ReRAM array. Afterwards, a second pulse is applied to the first ReRAM unit, wherein the electrical property of the first pulse is opposite to that of the second pulse. Then, a verification pulse is applied to the first ReRAM unit to verify whether the first resistance value of the first ReRAM unit passes a preset threshold. When the first resistance value passes the preset threshold value, a third pulse is applied to the first ReRAM unit, wherein the first pulse and the third pulse have the same electrical property, and the first pulse has a voltage value substantially the same to that of the third pulse.Type: GrantFiled: May 24, 2023Date of Patent: July 1, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsiu Hsu, Yu-Huan Yeh, Cheng-Hsiao Lai, Guan-Lin Chen, Chuan-Fu Wang, Hung-Yu Fan Chiang
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Publication number: 20250212426Abstract: A MIM capacitor structure includes a semiconductor substrate, and a first trench and a second trench in the semiconductor substrate in a capacitance forming region. The second trench is adjacent to the first trench. The second trench is deeper than the first trench. A dielectric liner layer conformally covers a top surface of the semiconductor substrate and interior surfaces of the first trench and the second trench. A bottom electrode layer conformally covers the dielectric liner layer. The bottom electrode layer extends onto a top surface of the semiconductor substrate. A capacitor dielectric layer is disposed on the bottom electrode layer in the first trench and the second trench. A top electrode layer is disposed on the capacitor dielectric layer in the first trench and the second trench. The top surface of the top electrode layer is coplanar with the top surface of the bottom electrode layer.Type: ApplicationFiled: January 10, 2024Publication date: June 26, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tai-Cheng Hou, Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai, Ya-Yin Hsiao, Po-Ching Su, Yi-Fan Li, Kuan-Jhih Hou, Yu-Fu Wang, Ti-Bin Chen, Chih-Chiang Wu, Yao-Jhan Wang
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Publication number: 20250191628Abstract: In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.Type: ApplicationFiled: February 18, 2025Publication date: June 12, 2025Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
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Publication number: 20250189786Abstract: Disclosed is a head-up display (HUD) architecture for a transport vehicle, including a transport vehicle front windshield structure and a display apparatus. The display apparatus is arranged on a side of the transport vehicle front windshield structure facing an interior of the transport vehicle and includes a display surface facing the transport vehicle front windshield structure. Image light is emitted by the display apparatus toward the transport vehicle front windshield structure in a propagation direction and reflected to an ocular point of a driver on the side of the transport vehicle front windshield structure facing the interior of the transport vehicle. A light emitting angle is defined between the propagation direction and a normal direction of the display surface. A peak value of intensity distribution of the light emitting angle is located outside the normal direction of the display surface.Type: ApplicationFiled: October 1, 2024Publication date: June 12, 2025Inventors: Yueh-Heng Lee, Chia-Hung Chen, Kuo-Yen Chang, Guang-Fu Wang, Yen-Ju Huang
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Publication number: 20250160226Abstract: An RRAM structure includes an RRAM. The RRAM includes a bottom electrode, a variable resistive layer and a top electrode stacked from bottom to top, wherein the bottom electrode is composed of titanium oxide (TiOx), 0<x?2, and x has a gradient variation increased toward the top electrode.Type: ApplicationFiled: December 7, 2023Publication date: May 15, 2025Applicant: UNITED MICROELECTRONICS CORPInventors: Wen-Jen Wang, Yu-Huan Yeh, Chuan-Fu Wang
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Publication number: 20250137773Abstract: A film thickness measurement device includes a spectroscopic ellipsometer, and the spectroscopic ellipsometer includes a projection module and a light receiving module. The projection module is configured to project a multi-wavelength polarized light onto a thin film. The projection module includes a light source and a polarization state generator. The light receiving module includes a polarization analyzer and an optical detector. The polarization analyzer is configured to screen out a multi-wavelength polarized reflection light according to reflection of the multi-wavelength polarized light by the thin film. The optical detector is configured to receive the multi-wavelength polarized reflection light. The optical detector includes at least one optical splitting unit, at least two optical filtering units and at least two optical detection units.Type: ApplicationFiled: December 13, 2023Publication date: May 1, 2025Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Shih-Hsiang LAI, Fu-Cheng YANG, Fu-Ching TUNG, Hsuan-Fu WANG, Po-Chun YEH
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Publication number: 20250133180Abstract: A teleprompter includes a connecting bracket, a prompting optical mechanism, a transferring board, and a supporting seat. The connecting bracket is used to support a monitor assembly. The prompting optical mechanism includes a main housing, a front frame, a rear frame, and a splitter. The transferring board is detachably connected to the rear frame. The transferring board has a photography opening. The supporting seat has an assembly board, and a horizontal carrier. The horizontal carrier is connected to a top end of the assembly board. The assembly board is connected to one side of the connecting bracket, and can be adjusted to different positions of the connecting bracket. Therefore, the horizontal carrier can be adjusted to different heights corresponding with the photography opening of the transferring board.Type: ApplicationFiled: February 21, 2024Publication date: April 24, 2025Inventors: YU-CHENG CHANG, CHIN-WEI HSU, SHANG-FU WANG, CHIA-HSIN TSAI
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Patent number: 12274350Abstract: A mobile device attachment adapted for a mobile device and a container for food or liquid is provided. The mobile device attachment includes a magnetic connecting member and a connecting member. The magnetic connecting member is selectively magnetically connected to the mobile device and adapted to extend in an escaping direction. The connecting member is disposed between the container and the magnetic connecting member. The mobile device has an image capturing range. When the magnetic connecting member extends in the escaping direction, the container, the magnetic connecting member and the connecting member are located outside the image capturing range. Besides, a container including the mobile device attachment is also provided.Type: GrantFiled: November 1, 2023Date of Patent: April 15, 2025Assignee: EVOLUTIVE LABS CO., LTD.Inventors: Ching-Fu Wang, Ching-Yu Wang, Che-Wei Hsu, Jui-Chen Lu, Cheng-Che Ho
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Publication number: 20250120230Abstract: An optical structure is provided. The optical structure includes a substrate, a light-emitting element, a glue layer, and a light-adjusting element. The light-emitting element is disposed on the substrate. The glue layer covers the light-emitting element. The light-adjusting element is disposed on the glue layer. Moreover, the refractive index of the glue layer is different from the refractive index of the light-adjusting element.Type: ApplicationFiled: August 21, 2024Publication date: April 10, 2025Inventors: Shu-Ching PENG, Yu-Hsi SUNG, Jung-Cheng CHANG, Wei-Chung CHENG, Yin-Cyuan WU, Sheng-Fu WANG, Wen-Yu LEE
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Publication number: 20250113495Abstract: A semiconductor device includes a resistive random access memory (RRAM) device, a dual damascene structure, and a spacer. The dual damascene structure is disposed near the RRAM device, and the spacer is disposed in a sidewall of the RRAM device. The RRAM device includes a lower electrode, a metal oxide layer, and an upper electrode. The metal oxide layer is disposed on the lower electrode, and the upper electrode is disposed on the metal oxide layer. The dual damascene structure includes a via and a wire disposed on the via, in which a top part of the wire is coplanar with a top part of the upper electrode in the RRAM device.Type: ApplicationFiled: October 26, 2023Publication date: April 3, 2025Applicant: United Microelectronics Corp.Inventors: Wen-Jen Wang, Yu-Huan Yeh, Chuan-Fu Wang
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Publication number: 20250098557Abstract: A resistive random access memory device includes a substrate; a dielectric layer disposed on the substrate; a conductive via disposed in the dielectric layer; a metal nitride layer disposed on the conductive via, wherein the metal nitride has a gradient nitrogen concentration along a thickness direction of the metal nitride layer; a resistive switching layer disposed on the metal nitride layer; and a metal oxynitride layer disposed on the resistive switching layer, wherein the metal oxynitride layer has a gradient nitrogen concentration along a thickness direction of the metal oxynitride layer.Type: ApplicationFiled: October 16, 2023Publication date: March 20, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kai-Jiun Chang, Yu-Huan Yeh, Chuan-Fu Wang
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Patent number: 12253474Abstract: A method and system for detecting the location of a surface defect on a transparent film with respect to whether the surface defect is at a front or back surface of the film. By illuminating the surface defect with a light source from an oblique angle and capturing an image of the surface defect using a camera which is positioned along an axis where the light illuminates after unobstructedly reflected from the test surface of the film, and using the reflected light, an image of the surface defect is obtained. A computer executes an evaluation logic to determine whether the image of the defect contains any dark area. If there is a dark area present, the defect is judged to be on the front surface of the film. If there is no dark area present, the defect is judged to be on the back surface of the film.Type: GrantFiled: March 27, 2023Date of Patent: March 18, 2025Assignee: HUA YANG Precision Machinery Co., LtdInventors: Hsien-Te Hsiao, Hsuan-Fu Wang
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Publication number: 20250081622Abstract: Semiconductor structures and formation processes thereof are provided. A semiconductor structure of the present disclosure includes a semiconductor substrate, a plurality of transistors disposed on the semiconductor substrate and comprising a plurality of gate structures extending lengthwise along a first direction, a metallization layer disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias, a dielectric layer over the metallization layer, a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer, a semiconductor layer disposed conformally over the plurality of dielectric fins, a source contact and a drain contact disposed directly on the semiconductor layer, and a gate structure disposed over the semiconductor layer and between the source contact and the drain contact.Type: ApplicationFiled: December 6, 2023Publication date: March 6, 2025Inventors: Hung-Li Chiang, Tsung-En Lee, Jer-Fu Wang, Chao-Ching Cheng, Iuliana Radu, Cheng-Chi Chuang, Chih-Sheng Chang, Ching-Wei Tsai
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Patent number: 12241844Abstract: A detection method and system for inspecting a defect on a semi-reflective film by way of different light sources illuminated on the semi-reflective film along the same axis. More specifically, a P-polarized light source and an S-polarized light source are used to illuminate the defect on the semi-reflective film, with an illumination direction that is between 5-45 degrees relative to the semi-reflective film. A camera module captures an image to be inspected through the phenomenon that the P-polarized light will partially pass through the semi-reflective film, and the S-polarized light will be almost completely reflected by the semi-reflective film. During the detection, the defect is determined to be located on the front surface of the semi-reflective film when the S-polarized light is present in the image, and the defect is determined to be located on the back surface of the semi-reflective film when the P-polarized light is present in the image and no S-polarized light has entered the camera module.Type: GrantFiled: March 27, 2023Date of Patent: March 4, 2025Assignee: HUA YANG Precision Machinery Co., LtdInventors: Hsien-Te Hsiao, Hsuan-Fu Wang
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Patent number: 12243619Abstract: In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.Type: GrantFiled: July 12, 2022Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
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Publication number: 20250072058Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a substrate, complex two-dimensional material layers disposed over the substrate, a gate structure and source and drain regions. The complex two-dimensional material layers are arranged spaced apart from one each other and in parallel to one another. The gate structure is disposed across and wraps around and surrounds first portions of the complex two-dimensional material layers. The source and drain regions are disposed on opposite sides of the gate structure and wrap around and surround second portions of the complex two-dimensional material layers.Type: ApplicationFiled: August 21, 2023Publication date: February 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jer-Fu Wang, Hung-Li Chiang, Goutham Arutchelvan, Wei-Sheng Yun, Chao-Ching Cheng, Iuliana Radu
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Publication number: 20250046372Abstract: A memory includes a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a first resistive memory element and a second resistive memory element. Each of the first switch transistor, the second switch transistor, the third switch transistor and the fourth switch transistor includes a drain terminal, a source terminal and a gate terminal. The drain terminal of the third switch transistor is coupled to the source terminal of the first switch transistor. The drain terminal of the fourth switch transistor is coupled to the source terminal of the second switch transistor. The first resistive memory element is coupled to the source terminal of the fourth switch transistor and the source terminal of the first switch transistor. The second resistive memory element is coupled to the source terminal of the third switch transistor and the source terminal of the second switch transistor.Type: ApplicationFiled: September 13, 2023Publication date: February 6, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shu-Hung Yu, Chuan-Fu Wang, Chung-Chin Shih
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Publication number: 20250048944Abstract: A resistive switching device includes a substrate, a first dielectric layer on the substrate, a conductive via in the first dielectric layer, and a resistive switching structure embedded in an upper portion of the conductive via. The resistive switching structure includes a top electrode layer having a lower sharp corner, a resistive switching material layer disposed around the lower sharp corner of the top electrode layer, and a bottom electrode layer disposed between the resistive switching material layer and the upper portion of the conductive via.Type: ApplicationFiled: August 25, 2023Publication date: February 6, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kai-Jiun Chang, Yu-Huan Yeh, Chuan-Fu Wang
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Publication number: 20250031380Abstract: A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.Type: ApplicationFiled: July 26, 2024Publication date: January 23, 2025Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang