Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.

Abstract: A method for detecting a particular syndrome based on hemodynamic analysis that includes steps of: obtaining a piece of hemodynamic data representing a hemodynamic waveform; performing moving average (MA) filtering on the hemodynamic waveform to obtain a filtered waveform; determining troughs in order to determine waveform segments of the filtered waveform; determining smoothness of the waveform segments; and determining a relation between the hemodynamic waveform and a particular syndrome based on the smoothness of the waveform segments, and generating a detection result.

Abstract: A method for detecting a particular syndrome based on hemodynamic analysis that includes steps of: obtaining a piece of hemodynamic data representing a hemodynamic waveform; performing moving average (MA) filtering on the hemodynamic waveform to obtain a filtered waveform; determining troughs in order to determine waveform segments of the filtered waveform; determining systolic peaks for determining first and second portions of the waveform segments; determining smoothness of the second portions; and determining a relation between the hemodynamic waveform and a particular syndrome based on the smoothness of the second portions, and generating a detection result.

Abstract: The disclosure provides a memory device, a method for configuring a first memory cell in an N-bit memory unit of a memory array, and a memory array. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.

Abstract: A memory device includes a transistor and a memory cell. The transistor includes a gate electrode disposed over a substrate and source/drain regions in the substrate beside the gate electrode. The memory cell is disposed over the transistor and includes a bottom electrode electrically connected to one of the source/drain regions, a top electrode disposed over the bottom electrode, and a first bit and a second bit separated from each other and disposed between the bottom electrode and the top electrode.

Abstract: A memory structure includes a substrate. The memory structure further includes a first transistor, wherein the first transistor is a first distance from the substrate. The memory structure further includes a second transistor, wherein the second transistor is a second distance from the substrate, and the first distance is different from the second distance, and a first source/drain (S/D) region of the first transistor is connected to a second S/D region of the second transistor. The memory structure further includes a plurality of storage elements electrically connected to both the first transistor and the second transistor, wherein each of the plurality of storage elements is a third distance from the substrate, and the third distance is different from both the first distance and the second distance.

Abstract: A method for detecting a location of a segment of a feeding tube is provided. The feeding tube has a proximal end, a hollow tube body and a distal end, and is placed inside the body of a patient. An audio collecting component is placed on a predetermined part of the patient. The method includes steps of pumping air into the proximal end of the feeding tube, collecting sound to obtain audio data by the audio collecting component, performing audio analysis on the audio data, and determining whether a segment of the hollow tube body is at a part inside the body of the patient that corresponds with the location of the audio collecting component based on result of the audio analysis.

Abstract: An integrated circuit device includes a first bit line structure that has a horizontal portion and a vertical portion in which an upper surface of the vertical portion is exposed for making electrical contact with a contact that, in turn, is in electrical contact with a metal pattern through which operating voltages may be applied to the bit line structure.

Abstract: Provided is a stainless steel powder composition, which comprises Cr, Cu, Mn, Mo, Ni and Fe; wherein, based on a total weight of the stainless steel powder composition, a content of Cr is 20 wt% to 24 wt%, and a content of Cu is more than 0 wt% and less than or equal to 0.5 wt%, a content of Mn is more than 0 wt% and less than or equal to 2 wt%, a content of Mo is 2.25 wt% to 3 wt% and a content of Ni is 10 wt% to 15 wt%. When applying the stainless steel powder composition of the present invention to laser additive manufacturing (LAM), the produced stainless steel workpiece has enhanced tensile strength, thereby expanding the follow-up applications and increasing the commercial value.

Abstract: A deposition apparatus including a chamber, a platform, a shower head, a bias power supply, a first injection device, and a second injection device is provided. The platform and the shower head are disposed in the chamber, and the platform is configured to carry a substrate having a high aspect ratio structure. The bias power supply is coupled to the platform. The first injection device and the second injection device are connected to the chamber; the first injection device injects a first precursor or a first inert gas into the chamber along a first direction through the shower head, and the second injection device injects a second precursor or a second inert gas into the chamber along a second direction perpendicular to the first direction. When the first precursor or the second precursor is injected into the chamber, the bias power supply is turned on. When the first inert gas or the second inert gas is injected into the chamber, the bias power supply is turned off. A deposition method is also provided.

Abstract: A method performed by a slave device to obtain a host memory address includes: inquiring a description list to obtain information of an allocated memory of a host; dividing the allocated memory into N storage spaces according to the information; using a first memory space of the N storage spaces to store a first level look-up table indicating physical addresses of the N storage spaces; dividing the first memory space into M storage spaces; storing a second level look-up table in the slave device to indicate physical addresses of the M storage spaces; inquiring the second level look-up table according to a logical address and obtaining a first index indicating a physical address of one of the M storage spaces; and inquiring the first level look-up table according to the first index and obtaining a second index indicating a physical address of one of the N storage spaces.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: A resistive memory device includes a bottom electrode, a switching layer including a first horizontal portion, a second horizontal portion over an upper surface of the bottom electrode, and a first vertical portion over a side surface of the bottom electrode, a top electrode including a first horizontal portion over the first horizontal portion of the switching layer, a second horizontal portion over the second horizontal portion of the switching layer, and a first vertical portion over the first vertical portion of the switching layer, and a conductive via contacting the first horizontal portion, the second horizontal portion and the first vertical portion of the top electrode. By providing a switching layer and a top electrode which conform to a non-planar profile of the bottom electrode, charge crowding and a localized increase in electric field may facilitate resistance-state switching and provide a reduced operating voltage.

Abstract: Described herein are compounds, compositions and methods useful for inhibiting Kelch-like ECH-associated protein 1 (KEAP1). The compounds, compositions and methods described herein are useful for treating diseases, disorders or conditions associated with KEAP1.

Abstract: The invention provides an iron-based metallic glass alloy powder including: Fe as the main component; a metalloid element group including Si, B, and C; a small amount of Mo to improve the degree-of-supercooling; and the addition of Cr and Ni to increase corrosion resistance, where the total amount of the metalloid element group, the amount of the degree-of-supercooling improvement element and the total amount of the elements to increase corrosion resistance are set within predetermined ranges.

Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.

Abstract: A connecting apparatus includes a main body having a first half member and a second half member; the second ends of the two half members configured to open or close relatively to each other; an accommodating cavity formed between the first and second half members; a driving member and an actuating member installed inside the accommodating cavity; the driving member capable of driving the actuating member to move toward the second ends of the two half members to an opened position, thereby expanding the second ends of the two half members outward. The connecting apparatus is installed inside an elongated member, and latch portions on the second ends of the two half members are able to latch onto another elongated member to achieve a connection between elongated members.

Abstract: A method of expanding natural killer cells, comprising: providing a population of internally gelated cells, each of which includes a gelated interior and a fluid cell membrane that contains one or more membrane-bound proteins each or collectively are capable of stimulating expansion of natural killer (NK) cells; and culturing a population of cells containing NK cells, which are capable of responding to the one or more membrane-bound proteins, with the population of internally gelated cells under conditions that allow expansion of NK cells.