Abstract: A resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.

Abstract: A combination toilet unblocking/cleaning apparatus for providing both a toilet unblocking and toilet cleaning tool in one convenient unit. The toilet unblocking tool further includes an adjustable auger, a combined tongs, and a detachable rod. Wherein, the adjustable auger includes two drain cleaning cable connected to a slider and slidable held in an elongated sleeve member; and the detachable rod is removably attached to the adjustable auger to form a combined tongs, constructed in such manner that the rod member can be used individually as drain rod. Also, the combination toilet cleaning tool is using the combined tongs as a handle with a plurality of different detachable bathroom accessories. Accessories may include a brush, a plunger, and a scraper; in which the brush, the plunger, and the scraper are configured to be selectively and removably coupled to the combined tongs.

Abstract: An electrical connector includes an insulating block and multiple terminals arranged along a left-right direction of the insulating block. The insulating block has multiple opening holes along a vertical direction thereof. Each terminal has a fixing portion fixed to the insulating block. The fixing portion has an adjustment portion. The terminals in one row include multiple first ground terminals, multiple second ground terminals and multiple pairs of differential signal terminals, correspondingly arranged along the left-right direction sequentially as: one of the first ground terminals, one of the pairs of differential signal terminals, one of the second ground terminals, another one of the pairs of differential signal terminals, and another one of the first ground terminals. The adjustment portion of each second ground terminal is exposed in the opening hole along the vertical direction, and the adjustment portion of each first ground terminal is not exposed in the opening hole.

Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.

Abstract: An electrical module is electrically conducted with an electronic component, and includes multiple conductors having a first row of conductors arranged in a left-right direction and an insulating body fixing the first row of conductors. Each conductor has a contact portion in contact with the electronic component. A distance between each two adjacent contact portions of the conductors in the left-right direction is defined as a contact interval. The first row of conductors have at least one pair of signal conductors and at least two ground conductors. Each two adjacent sides of the pair of signal conductors has one ground conductor. The contact interval from one signal conductor to its adjacent ground conductor is defined as a first contact interval. The contact interval from the other signal conductor to its adjacent ground conductor is defined as a second contact interval. The first and second contact intervals are not equal.

Abstract: An electrical connector electrically connects a first electrical module and a second electrical module, for insertion by the first electrical module along a first direction. The electrical connector includes a first group of terminals arranged in a row along a second direction, having multiple signal terminals and multiple ground terminals and forming at least one first terminal unit and at least one second terminal unit. Each of the terminals has a contact portion, a tail portion, and a middle portion located between the contact portion and the tail portion. In the second direction, the middle portions of the first terminal unit form a first row of the middle portions, and the middle portions of the second terminal unit form a second row of the middle portions. Viewing from the second direction, the first and second rows of the middle portions are staggered, thus improving the crosstalk.

Abstract: A memory device structure includes a substrate, a memory stacked structure, and a spacer. The memory stacked structure is formed on the substrate by stacking a first electrode layer, a memory material layer, and a second electrode layer. The memory material layer has a tilted sidewall, or the memory material layer and the first electrode layer have a tilted sidewall. The tilted sidewall is indented with respect to a sidewall of the second electrode layer. The spacer is disposed on the tilted sidewall.

Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.

Abstract: A resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.