Abstract: A method of expanding natural killer cells, comprising: providing a population of internally gelated cells, each of which includes a gelated interior and a fluid cell membrane that contains one or more membrane-bound proteins each or collectively are capable of stimulating expansion of natural killer (NK) cells; and culturing a population of cells containing NK cells, which are capable of responding to the one or more membrane-bound proteins, with the population of internally gelated cells under conditions that allow expansion of NK cells.

Abstract: A combination toilet unblocking/cleaning apparatus for providing both a toilet unblocking and toilet cleaning tool in one convenient unit. The toilet unblocking tool further includes an adjustable auger, a combined tongs, and a detachable rod. Wherein, the adjustable auger includes two drain cleaning cable connected to a slider and slidable held in an elongated sleeve member; and the detachable rod is removably attached to the adjustable auger to form a combined tongs, constructed in such manner that the rod member can be used individually as drain rod. Also, the combination toilet cleaning tool is using the combined tongs as a handle with a plurality of different detachable bathroom accessories. Accessories may include a brush, a plunger, and a scraper; in which the brush, the plunger, and the scraper are configured to be selectively and removably coupled to the combined tongs.

Abstract: Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a first dielectric pattern, a second dielectric pattern, a first bottom electrode, a first storage pattern, and a first top electrode. The first bottom electrode is disposed between the first dielectric pattern and the second dielectric pattern, and the first bottom electrode interfaces a first sidewall of the first dielectric pattern and a sidewall of the second dielectric pattern. The first storage pattern is disposed on the first dielectric pattern, the second dielectric pattern and the first bottom electrode, wherein the first storage pattern is electrically connected to the first bottom electrode. The first storage pattern is between the first bottom electrode and the first top electrode. A semiconductor die including a memory array is also provided.

Abstract: The present disclosure is a wafer support, which includes a heating unit, an insulating-and-heat-conducting unit and a conduct portion, wherein the insulating-and-heat-conducting unit is positioned between the conduct portion and the heating unit. During a deposition process, an AC bias is formed on the conduct portion to attract a plasma disposed thereabove. The heating unit includes at least one heating coil, wherein the heating coil heats the wafer supported by the wafer support via the insulating-and-heat-conducting unit and the conduct portion. The insulating-and-heat-conducting unit electrically insulates the heating unit and the conduct portion to prevent the AC flowing in the heating coil and the AC bias on the conduct portion from conducting each other, so the wafer support can generate a stable AC bias and temperature to facilitate forming an evenly-distributed thin film on the wafer supported by the wafer support.

Abstract: A ReRAM device includes a dielectric layer, a bottom electrode, a data storage layer, a metal covering layer, and a top electrode. The dielectric layer has a recess. At least a portion of the bottom electrode is exposed through the recess. The data storage layer is disposed on a sidewall and a bottom surface of the recess, electrically contacts with the bottom electrode, and has a top portion lower than an opening of the recess. The metal covering layer blanket covers the data storage layer, has an extension portion covering the top portion, and connects to the sidewall of the recess. The top electrode is disposed in the recess, and is electrically contact with the metal covering layer.

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

Abstract: A system for adding an external function to a webpage includes: one or more processors; and memory communicably connected to the one or more processors and storing instructions that, when executed by the one or more processors, cause the one or more processors to: receive code associated with the webpage from a remote server; identify a plurality of images in the code; filter the plurality of images to identify a first type of image different from other images of the plurality of images; and append the external function to the first type of image to display a modified webpage including the external function on a display device of a first user.

Abstract: Provided are a resistive random access memory (RRAM) and a manufacturing method thereof. The resistive random access memory includes multiple unit structures disposed on a substrate. Each of the unit structures includes a first electrode, a first metal oxide layer, and a spacer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. The spacer is disposed on sidewalls of the first electrode and the first metal oxide layer. In addition, the resistive random access memory includes a second metal oxide layer and a second electrode. The second metal oxide layer is disposed on the unit structures and is connected to the unit structures. The second electrode is disposed on the second metal oxide layer.

Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.

Abstract: A resistive random-access memory (RRAM) device, including a bottom electrode, a high work function layer, a resistive material layer and a top electrode sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part, first spacers covering sidewalls of the top part and the top electrode, and second spacers covering sidewalls of the bottom part, thereby constituting a RRAM cell.

Abstract: A method includes forming a fin protruding from a semiconductor substrate; forming a dummy gate stack over the fin, wherein forming the dummy gate stack includes depositing a layer of amorphous material over the fin; performing an anneal process on the layer of amorphous material, wherein the anneal process recrystallizes the layer of amorphous material into a layer of polycrystalline material, wherein the anneal process includes heating the layer of amorphous material for less than one millisecond; and patterning the layer of polycrystalline material; and forming an epitaxial source/drain region in the fin adjacent the dummy gate stack; and removing the dummy gate stack and replacing the dummy gate stack with a replacement gate stack.

Abstract: The present disclosure provides an accessory for a handheld device. The accessory includes a first base, a second base, a first flexible element and a second flexible element. The first flexible element and the second flexible element are respectively disposed at the first base. The first flexible element has a first track. The second flexible element has a second track. The second base has a fastener for engaging with the first track and the second track. The first flexible element is flexed based on sliding of the fastener along the first track. The second flexible element is flexed based on sliding of the fastener along the second track.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

Abstract: A method for forming a resistive random access memory structure. The resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.

Abstract: A RRAM device includes a bottom electrode, a resistive material layer, a high work function layer, a top electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the high work function layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming said RRAM device is also provided.

Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.