Abstract: An integrated circuit device includes a first bit line structure that has a horizontal portion and a vertical portion in which an upper surface of the vertical portion is exposed for making electrical contact with a contact that, in turn, is in electrical contact with a metal pattern through which operating voltages may be applied to the bit line structure.

Abstract: Provided is a stainless steel powder composition, which comprises Cr, Cu, Mn, Mo, Ni and Fe; wherein, based on a total weight of the stainless steel powder composition, a content of Cr is 20 wt% to 24 wt%, and a content of Cu is more than 0 wt% and less than or equal to 0.5 wt%, a content of Mn is more than 0 wt% and less than or equal to 2 wt%, a content of Mo is 2.25 wt% to 3 wt% and a content of Ni is 10 wt% to 15 wt%. When applying the stainless steel powder composition of the present invention to laser additive manufacturing (LAM), the produced stainless steel workpiece has enhanced tensile strength, thereby expanding the follow-up applications and increasing the commercial value.

Abstract: A deposition apparatus including a chamber, a platform, a shower head, a bias power supply, a first injection device, and a second injection device is provided. The platform and the shower head are disposed in the chamber, and the platform is configured to carry a substrate having a high aspect ratio structure. The bias power supply is coupled to the platform. The first injection device and the second injection device are connected to the chamber; the first injection device injects a first precursor or a first inert gas into the chamber along a first direction through the shower head, and the second injection device injects a second precursor or a second inert gas into the chamber along a second direction perpendicular to the first direction. When the first precursor or the second precursor is injected into the chamber, the bias power supply is turned on. When the first inert gas or the second inert gas is injected into the chamber, the bias power supply is turned off. A deposition method is also provided.

Abstract: A method performed by a slave device to obtain a host memory address includes: inquiring a description list to obtain information of an allocated memory of a host; dividing the allocated memory into N storage spaces according to the information; using a first memory space of the N storage spaces to store a first level look-up table indicating physical addresses of the N storage spaces; dividing the first memory space into M storage spaces; storing a second level look-up table in the slave device to indicate physical addresses of the M storage spaces; inquiring the second level look-up table according to a logical address and obtaining a first index indicating a physical address of one of the M storage spaces; and inquiring the first level look-up table according to the first index and obtaining a second index indicating a physical address of one of the N storage spaces.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: A resistive memory device includes a bottom electrode, a switching layer including a first horizontal portion, a second horizontal portion over an upper surface of the bottom electrode, and a first vertical portion over a side surface of the bottom electrode, a top electrode including a first horizontal portion over the first horizontal portion of the switching layer, a second horizontal portion over the second horizontal portion of the switching layer, and a first vertical portion over the first vertical portion of the switching layer, and a conductive via contacting the first horizontal portion, the second horizontal portion and the first vertical portion of the top electrode. By providing a switching layer and a top electrode which conform to a non-planar profile of the bottom electrode, charge crowding and a localized increase in electric field may facilitate resistance-state switching and provide a reduced operating voltage.

Abstract: Described herein are compounds, compositions and methods useful for inhibiting Kelch-like ECH-associated protein 1 (KEAP1). The compounds, compositions and methods described herein are useful for treating diseases, disorders or conditions associated with KEAP1.

Abstract: The invention provides an iron-based metallic glass alloy powder including: Fe as the main component; a metalloid element group including Si, B, and C; a small amount of Mo to improve the degree-of-supercooling; and the addition of Cr and Ni to increase corrosion resistance, where the total amount of the metalloid element group, the amount of the degree-of-supercooling improvement element and the total amount of the elements to increase corrosion resistance are set within predetermined ranges.

Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.

Abstract: A connecting apparatus includes a main body having a first half member and a second half member; the second ends of the two half members configured to open or close relatively to each other; an accommodating cavity formed between the first and second half members; a driving member and an actuating member installed inside the accommodating cavity; the driving member capable of driving the actuating member to move toward the second ends of the two half members to an opened position, thereby expanding the second ends of the two half members outward. The connecting apparatus is installed inside an elongated member, and latch portions on the second ends of the two half members are able to latch onto another elongated member to achieve a connection between elongated members.

Abstract: A method of expanding natural killer cells, comprising: providing a population of internally gelated cells, each of which includes a gelated interior and a fluid cell membrane that contains one or more membrane-bound proteins each or collectively are capable of stimulating expansion of natural killer (NK) cells; and culturing a population of cells containing NK cells, which are capable of responding to the one or more membrane-bound proteins, with the population of internally gelated cells under conditions that allow expansion of NK cells.

Abstract: A combination toilet unblocking/cleaning apparatus for providing both a toilet unblocking and toilet cleaning tool in one convenient unit. The toilet unblocking tool further includes an adjustable auger, a combined tongs, and a detachable rod. Wherein, the adjustable auger includes two drain cleaning cable connected to a slider and slidable held in an elongated sleeve member; and the detachable rod is removably attached to the adjustable auger to form a combined tongs, constructed in such manner that the rod member can be used individually as drain rod. Also, the combination toilet cleaning tool is using the combined tongs as a handle with a plurality of different detachable bathroom accessories. Accessories may include a brush, a plunger, and a scraper; in which the brush, the plunger, and the scraper are configured to be selectively and removably coupled to the combined tongs.

Abstract: Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a first dielectric pattern, a second dielectric pattern, a first bottom electrode, a first storage pattern, and a first top electrode. The first bottom electrode is disposed between the first dielectric pattern and the second dielectric pattern, and the first bottom electrode interfaces a first sidewall of the first dielectric pattern and a sidewall of the second dielectric pattern. The first storage pattern is disposed on the first dielectric pattern, the second dielectric pattern and the first bottom electrode, wherein the first storage pattern is electrically connected to the first bottom electrode. The first storage pattern is between the first bottom electrode and the first top electrode. A semiconductor die including a memory array is also provided.

Abstract: The present disclosure is a wafer support, which includes a heating unit, an insulating-and-heat-conducting unit and a conduct portion, wherein the insulating-and-heat-conducting unit is positioned between the conduct portion and the heating unit. During a deposition process, an AC bias is formed on the conduct portion to attract a plasma disposed thereabove. The heating unit includes at least one heating coil, wherein the heating coil heats the wafer supported by the wafer support via the insulating-and-heat-conducting unit and the conduct portion. The insulating-and-heat-conducting unit electrically insulates the heating unit and the conduct portion to prevent the AC flowing in the heating coil and the AC bias on the conduct portion from conducting each other, so the wafer support can generate a stable AC bias and temperature to facilitate forming an evenly-distributed thin film on the wafer supported by the wafer support.

Abstract: A ReRAM device includes a dielectric layer, a bottom electrode, a data storage layer, a metal covering layer, and a top electrode. The dielectric layer has a recess. At least a portion of the bottom electrode is exposed through the recess. The data storage layer is disposed on a sidewall and a bottom surface of the recess, electrically contacts with the bottom electrode, and has a top portion lower than an opening of the recess. The metal covering layer blanket covers the data storage layer, has an extension portion covering the top portion, and connects to the sidewall of the recess. The top electrode is disposed in the recess, and is electrically contact with the metal covering layer.

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

Abstract: A system for adding an external function to a webpage includes: one or more processors; and memory communicably connected to the one or more processors and storing instructions that, when executed by the one or more processors, cause the one or more processors to: receive code associated with the webpage from a remote server; identify a plurality of images in the code; filter the plurality of images to identify a first type of image different from other images of the plurality of images; and append the external function to the first type of image to display a modified webpage including the external function on a display device of a first user.