Abstract: A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.

Abstract: The present disclosure is a wafer support, which includes a heating unit, an insulating-and-heat-conducting unit and a conduct portion, wherein the insulating-and-heat-conducting unit is positioned between the conduct portion and the heating unit. During a deposition process, an AC bias is formed on the conduct portion to attract a plasma disposed thereabove. The heating unit includes at least one heating coil, wherein the heating coil heats the wafer supported by the wafer support via the insulating-and-heat-conducting unit and the conduct portion. The insulating-and-heat-conducting unit electrically insulates the heating unit and the conduct portion to prevent the AC flowing in the heating coil and the AC bias on the conduct portion from conducting each other, so the wafer support can generate a stable AC bias and temperature to facilitate forming an evenly-distributed thin film on the wafer supported by the wafer support.

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a first dielectric pattern, a second dielectric pattern, a first bottom electrode, a first storage pattern, and a first top electrode. The first bottom electrode is disposed between the first dielectric pattern and the second dielectric pattern, and the first bottom electrode interfaces a first sidewall of the first dielectric pattern and a sidewall of the second dielectric pattern. The first storage pattern is disposed on the first dielectric pattern, the second dielectric pattern and the first bottom electrode, wherein the first storage pattern is electrically connected to the first bottom electrode. The first storage pattern is between the first bottom electrode and the first top electrode. A semiconductor die including a memory array is also provided.

Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming said resistive random access memory (RRAM) structure is also provided.

Abstract: A wafer holder for generating a stable bias voltage, which mainly includes a holder, a ring member, and a cover ring, wherein a supporting surface of the holder is used to carry at least one wafer, and the ring member is arranged on the holder and located around the supporting surface and the wafer. The ring member includes an outer surface and an inner surface, wherein the inner surface of the ring member covers a part of the side surface of the holder and makes parts of the side surface exposed. When the cover ring is connected to the ring member, a shielding portion of the cover ring will cover the exposed side surface of the holder to avoid a film being formed on the exposed side surface of the holder to facilitate the formation of a uniform and stable bias voltage on the wafer holder.

Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.

Abstract: A method for exchanging messages is performed by a slave device, and includes: receiving a submission queue (SQ) tail doorbell from a host to learn that X SQ entries need to be processed, wherein “X” doesn't exceed a host SQ entry upper limit; performing multiple read operations according to the SQ tail doorbell to read the X SQ entries from the host, wherein the slave device reads Y SQ entries at most in each read operation, and “Y” is smaller than “X” and doesn't exceed a slave device SQ entry upper limit; preparing P completion queue (CQ) entries; performing multiple write operations to transmit the P CQ entries to the host, wherein the slave device transmits Q CQ entries at most in each write operation, and “Q” is smaller than “P” and doesn't exceed a slave device CQ entry upper limit; and transmitting a CQ tail doorbell to the host.

Abstract: Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.

Abstract: A method performed by a slave device to obtain a host memory address includes: inquiring a description list to obtain information of an allocated memory of a host; dividing the allocated memory into N storage spaces according to the information; using a first memory space of the N storage spaces to store a first level look-up table indicating physical addresses of the N storage spaces; dividing the first memory space into M storage spaces; storing a second level look-up table in the slave device to indicate physical addresses of the M storage spaces; inquiring the second level look-up table according to a logical address and obtaining a first index indicating a physical address of one of the M storage spaces; and inquiring the first level look-up table according to the first index and obtaining a second index indicating a physical address of one of the N storage spaces.

Abstract: Provided is a platinum complex having a structure represented by formula (I): wherein A1 to A3 each independently represent a 5-membered or 6-membered unsaturated ring, A3 is optionally formed between A1 and A2; X1, X2, and X3 each independently represent carbon or nitrogen; R1 represents hydrogen, substituted or unsubstituted C1-C6 alkyl, —CF2H, —CFH2, substituted or unsubstituted C6-C12 aryl or —CmF2m+1, m is an integer of 1 to 5; R2 and R3 each independently represent hydrogen, C1-C12 alkyl, substituted or unsubstituted C1-C6 alkoxyl, substituted or unsubstituted C6-C12 aryl, or —CnF2n+1, n is an integer of 0 to 3; p and q each independently represent an integer of 1 to 2; and when p or q is equal to 2, two R2's or R3's may join to form a C3-C8 aromatic or nitrogen-containing heteroaromatic ring.

Abstract: A composite button is configured to be inserted into a button hole of a protective case for contacting a trigger button of an electronic device. The protective case includes a casing peripheral wall having an inner peripheral surface. The composite button includes a soft material layer having a contact surface suitable for contacting the trigger button, and a soft material connecting surface opposite to said contact surface. A hard material layer is connected to said soft material connecting surface. At least one of the soft and hard material layers has a peripheral flange suitable for abutting against the inner peripheral surface of the casing peripheral wall.

Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.

Abstract: A touch display device includes a cover plate, a touch module, a frame, and a display module. The touch module is disposed on the cover plate and defines thereon a sensing zone and a peripheral zone connecting each other. The frame is located at a side of the touch module away from the cover plate and includes a plurality of fixing members and an accommodating trough. The fixing members cross the peripheral zone to be fixed to the cover plate. At least one part of the touch module in the peripheral zone is attached to a side of the frame away from the cover plate. The display module is disposed in the accommodating trough and over the sensing zone.

Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are formed in the first dielectric layer and respectively on the memory region and the logic region of the substrate. A memory cell is disposed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer is formed on the first dielectric layer and continuously covers a top surface and a sidewall of the memory cell and a top surface of the second conductive structure. A second dielectric layer is formed on the first cap. A third conductive structure is formed in the second dielectric layer and penetrates through the first cap layer to contacts the memory cell.

Abstract: A particles capturing system includes a venturi filter device, a cyclone filter device, a plurality of first nozzles and air to flow through the system. The venturi filter device has an air intake portion, a neck portion and an air outlet portion. The cyclone filter device, disposed in the air outlet portion, has an entrance and an exit. The plurality of first nozzles, disposed inside the venturi filter device, have a height greater than that of the the neck portion. When the air flows, the air enters the venturi filter device via an air inlet of the air intake portion, then orderly passes through the neck portion and the plurality of first nozzles, then enters the cyclone filter device via the entrance, and finally leaves the cyclone filter device via the exit, such that particles in the flowing air can be captured.

Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.

Abstract: A touch display device includes a cover plate, a touch module, a frame, and a display module. The touch module is disposed on the cover plate and defines thereon a sensing zone and a peripheral zone connecting each other. The frame is located at a side of the touch module away from the cover plate and includes a plurality of fixing members and an accommodating trough. The fixing members cross the peripheral zone to be fixed to the cover plate. At least one part of the touch module in the peripheral zone is attached to a side of the frame away from the cover plate. The display module is disposed in the accommodating trough and over the sensing zone.

Abstract: An electrical connector includes an insulating block and multiple terminals arranged along a left-right direction of the insulating block. The insulating block has multiple opening holes along a vertical direction thereof. Each terminal has a fixing portion fixed to the insulating block. The fixing portion has an adjustment portion. The terminals in one row include multiple first ground terminals, multiple second ground terminals and multiple pairs of differential signal terminals, correspondingly arranged along the left-right direction sequentially as: one of the first ground terminals, one of the pairs of differential signal terminals, one of the second ground terminals, another one of the pairs of differential signal terminals, and another one of the first ground terminals. The adjustment portion of each second ground terminal is exposed in the opening hole along the vertical direction, and the adjustment portion of each first ground terminal is not exposed in the opening hole.