Patents by Inventor Fu Wang

Fu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11233196
    Abstract: A memory device structure includes a substrate, a memory stacked structure, and a spacer. The memory stacked structure is formed on the substrate by stacking a first electrode layer, a memory material layer, and a second electrode layer. The memory material layer has a tilted sidewall, or the memory material layer and the first electrode layer have a tilted sidewall. The tilted sidewall is indented with respect to a sidewall of the second electrode layer. The spacer is disposed on the tilted sidewall.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: January 25, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20220007936
    Abstract: The present invention provides a neurological disorders decision support system that can assist an examiner to diagnose an examinee. The neurological disorders decision support system includes a user module, a screening module, an intelligent calculation module and a diagnosis module. The user module sends an inquiry to the examinee, receives a response message from the examinee, and retrieves a physiological characteristic signal of the examinee. The screening module executes a neurological examination application program to indicate to the examinee to obtain physiological characteristic signals. The screening module outputs response messages and physiological characteristic signals for the intelligent calculation module to execute an algorithm to generate an analysis report. The analysis report assists the examiner for diagnosis, and sends a diagnosis notification to the user module through the diagnosis module. The invention also provides a neurological disorders decision support method.
    Type: Application
    Filed: July 13, 2020
    Publication date: January 13, 2022
    Inventors: Chun-Chen YANG, Ching-Fu WANG, Chin-Hsun HUANG, Wei-Cheng CHEN
  • Patent number: 11196219
    Abstract: An electrical connector electrically connects a first electrical module and a second electrical module, for insertion by the first electrical module along a first direction. The electrical connector includes a first group of terminals arranged in a row along a second direction, having multiple signal terminals and multiple ground terminals and forming at least one first terminal unit and at least one second terminal unit. Each of the terminals has a contact portion, a tail portion, and a middle portion located between the contact portion and the tail portion. In the second direction, the middle portions of the first terminal unit form a first row of the middle portions, and the middle portions of the second terminal unit form a second row of the middle portions. Viewing from the second direction, the first and second rows of the middle portions are staggered, thus improving the crosstalk.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: December 7, 2021
    Assignee: LOTES CO., LTD
    Inventors: Qi Xiao Yang, Yong Fu Wang
  • Publication number: 20210336133
    Abstract: A method for forming a resistive random access memory structure. The resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.
    Type: Application
    Filed: July 9, 2021
    Publication date: October 28, 2021
    Inventors: Wen-Jen WANG, Chun-Hung CHENG, Chuan-Fu WANG
  • Patent number: 11139618
    Abstract: An electrical module is electrically conducted with an electronic component, and includes multiple conductors having a first row of conductors arranged in a left-right direction and an insulating body fixing the first row of conductors. Each conductor has a contact portion in contact with the electronic component. A distance between each two adjacent contact portions of the conductors in the left-right direction is defined as a contact interval. The first row of conductors have at least one pair of signal conductors and at least two ground conductors. Each two adjacent sides of the pair of signal conductors has one ground conductor. The contact interval from one signal conductor to its adjacent ground conductor is defined as a first contact interval. The contact interval from the other signal conductor to its adjacent ground conductor is defined as a second contact interval. The first and second contact intervals are not equal.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: October 5, 2021
    Assignee: LOTES CO., LTD
    Inventors: Qi Xiao Yang, Yong Fu Wang, Wei Xue Zhong, Biao Zhang, Jia Xu Yin
  • Publication number: 20210297105
    Abstract: The present disclosure provides a protection case assembly for a handheld device. The protection case assembly includes a main case and a frame. The main case has an accommodating space configured to accommodate the handheld device, and an opening disposed correspondingly to a lens module of the handheld device. The frame is detachably disposed in the opening, and includes a groove set configured to receive the main case in the opening.
    Type: Application
    Filed: July 13, 2020
    Publication date: September 23, 2021
    Inventors: CHING-FU WANG, SHENG-CHE SU, PO-WEN HSIAO, CHIA-HO LIN
  • Publication number: 20210257258
    Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.
    Type: Application
    Filed: July 27, 2020
    Publication date: August 19, 2021
    Inventors: Wen-Hung Huang, Kuo-Feng Yu, Jian-Hao Chen, Shan-Mei Liao, Jer-Fu Wang, Yung-Hsiang Chan
  • Patent number: 11094880
    Abstract: A resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 17, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20210222419
    Abstract: A combination toilet unblocking/cleaning apparatus for providing both a toilet unblocking and toilet cleaning tool in one convenient unit. The toilet unblocking tool further includes an adjustable auger, a combined tongs, and a detachable rod. Wherein, the adjustable auger includes two drain cleaning cable connected to a slider and slidable held in an elongated sleeve member; and the detachable rod is removably attached to the adjustable auger to form a combined tongs, constructed in such manner that the rod member can be used individually as drain rod. Also, the combination toilet cleaning tool is using the combined tongs as a handle with a plurality of different detachable bathroom accessories. Accessories may include a brush, a plunger, and a scraper; in which the brush, the plunger, and the scraper are configured to be selectively and removably coupled to the combined tongs.
    Type: Application
    Filed: January 18, 2020
    Publication date: July 22, 2021
    Inventor: CHI FU WANG
  • Publication number: 20210218169
    Abstract: An electrical connector includes an insulating block and multiple terminals arranged along a left-right direction of the insulating block. The insulating block has multiple opening holes along a vertical direction thereof. Each terminal has a fixing portion fixed to the insulating block. The fixing portion has an adjustment portion. The terminals in one row include multiple first ground terminals, multiple second ground terminals and multiple pairs of differential signal terminals, correspondingly arranged along the left-right direction sequentially as: one of the first ground terminals, one of the pairs of differential signal terminals, one of the second ground terminals, another one of the pairs of differential signal terminals, and another one of the first ground terminals. The adjustment portion of each second ground terminal is exposed in the opening hole along the vertical direction, and the adjustment portion of each first ground terminal is not exposed in the opening hole.
    Type: Application
    Filed: August 25, 2020
    Publication date: July 15, 2021
    Inventors: Qi Xiao Yang, Ming Jiang, Yong Fu Wang
  • Publication number: 20210217813
    Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.
    Type: Application
    Filed: February 18, 2020
    Publication date: July 15, 2021
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20210159642
    Abstract: An electrical module is electrically conducted with an electronic component, and includes multiple conductors having a first row of conductors arranged in a left-right direction and an insulating body fixing the first row of conductors. Each conductor has a contact portion in contact with the electronic component. A distance between each two adjacent contact portions of the conductors in the left-right direction is defined as a contact interval. The first row of conductors have at least one pair of signal conductors and at least two ground conductors. Each two adjacent sides of the pair of signal conductors has one ground conductor. The contact interval from one signal conductor to its adjacent ground conductor is defined as a first contact interval. The contact interval from the other signal conductor to its adjacent ground conductor is defined as a second contact interval. The first and second contact intervals are not equal.
    Type: Application
    Filed: June 11, 2020
    Publication date: May 27, 2021
    Inventors: Qi Xiao Yang, Yong Fu Wang, Wei Xue Zhong, Biao Zhang, Jia Xu Yin
  • Patent number: D920167
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 25, 2021
    Assignee: Gogoro Inc.
    Inventors: Sung-Fu Wang, Hsin-Wen Su, Chien-Chih Weng, Hsi-Wen Chen, Ching-Chang Ni
  • Patent number: D920172
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 25, 2021
    Assignee: Gogoro Inc.
    Inventors: Sung-Fu Wang, Hsin-Wen Su, Chien-Chih Weng, Hsi-Wen Chen, Ching-Chang Ni
  • Patent number: D920200
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 25, 2021
    Assignee: Gogoro Inc.
    Inventors: Sung-Fu Wang, Hsin-Wen Su, Chien-Chih Weng, Hsi-Wen Chen, Ching-Chang Ni
  • Patent number: D920851
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 1, 2021
    Assignee: Gogoro Inc.
    Inventors: Sung-Fu Wang, Hsin-Wen Su, Chien-Chih Weng, Hsi-Wen Chen, Ching-Chang Ni
  • Patent number: D928040
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 17, 2021
    Assignee: Gogoro Inc.
    Inventors: Hok-Sum Horace Luke, Song-Fu Wang, Hsin-Wen Su, Hsi-Wen Chen, Chien-Chih Weng
  • Patent number: D928666
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 24, 2021
    Assignee: Gogoro Inc.
    Inventors: Hok-Sum Horace Luke, Song-Fu Wang, Hsin-Wen Su, Hsi-Wen Chen, Chien-Chih Weng
  • Patent number: D931273
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: September 21, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Jui-Lung Wang, Chang-Ta Miao, Chu-Fu Wang, Gwo-Chyuan Chen
  • Patent number: D934848
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: November 2, 2021
    Assignee: Evolutive Labs Co., Ltd.
    Inventor: Ching-Fu Wang