Abstract: A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.

Abstract: A display panel includes a substrate, light-emitting diodes, and a cured opaque encapsulant layer. The light-emitting diodes are disposed on a first surface of the substrate. The cured opaque encapsulant layer is disposed on the first surface and a side surface of the substrate, and surrounds the light emitting diodes. A second surface of the cured opaque encapsulant layer facing away from the substrate is a rough surface.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first semiconductor layer overlying a substrate. A first barrier layer is disposed on the first semiconductor layer. A second semiconductor layer overlies and directly contacts the first barrier layer. A second barrier layer directly contacts the first barrier layer. A third semiconductor layer overlies the second barrier layer. A fourth semiconductor layer overlies the third semiconductor layer. Outer sidewalls of the third semiconductor layer, outer sidewalls of the fourth semiconductor layer, and outer sidewalls of the second barrier layer are respectively aligned.

Abstract: A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.

Abstract: The transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer.

Abstract: An aspect of the disclosure includes a communication system and a communication method using reconfigurable intelligent surface and a reconfigurable intelligent surface device. The communication system includes at least one base station, a reconfigurable intelligent surface device, and a control at one least device. The at least one base station respectively transmits at least one beam. The reconfigurable intelligent surface device is coupled to the at least one base station, and measures the at least one beam of the at least one base station to obtain signal measurement results associated with each of the at least one base station. The control device is coupled to the at least one base station. The control device groups the at least one base station and the reconfigurable intelligent surface device into at least one group according to the signal measurement results associated with each of the at least one base station.

Abstract: A covering film (100) includes a first covering layer (10), a first adhesive layer (20), and a thermal conductive layer (30) sandwiched between the first covering layer (10) and the first adhesive layer (20). A thermal conductivity of the thermal conductive layer (30) is K1, K1 is in a range of 3 W/m.K to 65 W/m.K. A thermal conductivity of the first covering layer (10) is K2, K2 is in a range of 0.02 W/m.K to 3.0 W/m.K. A thermal conductivity of the first adhesive layer (20) is K3, K3 is in a range of 0.02 W/m.K to 1.0 W/m.K. A circuit board and its manufacturing method are also provided.

Abstract: An aspect of the disclosure includes a communication system and a communication method using reconfigurable intelligent surface and a reconfigurable intelligent surface device. The communication system includes at least one base station, a reconfigurable intelligent surface device, and a control at one least device. The at least one base station respectively transmits at least one beam. The reconfigurable intelligent surface device is coupled to the at least one base station, and measures the at least one beam of the at least one base station to obtain signal measurement results associated with each of the at least one base station. The control device is coupled to the at least one base station. The control device groups the at least one base station and the reconfigurable intelligent surface device into at least one group according to the signal measurement results associated with each of the at least one base station.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a chip structure including a substrate and a wiring structure over a first surface of the substrate. The semiconductor device structure includes a first seed layer over the wiring structure, a first inner wall of the first enlarged portion, and a second inner wall of the neck portion. The semiconductor device structure includes a second seed layer over a second surface of the substrate, a third inner wall of the second enlarged portion, and the first seed layer over the second inner wall of the neck portion. The second seed layer is in direct contact with the first seed layer.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are presented. In embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. The first bonding layer and the semiconductor substrate are patterned to form first openings. A second substrate is bonded to the first substrate. After the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. After the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.

Abstract: A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.

Abstract: A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.

Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a chip structure including a substrate and a wiring structure over a first surface of the substrate. The method includes removing a first portion of the wiring structure adjacent to the hole to widen a second portion of the hole in the wiring structure. The second portion has a first width increasing in a first direction away from the substrate. The method includes forming a first seed layer over the wiring structure and in the hole. The method includes thinning the substrate from a second surface of the substrate until the first seed layer in the hole is exposed. The method includes forming a second seed layer over the second surface of the substrate and the first seed layer in the hole.

Abstract: A semiconductor device includes a substrate, one or more wiring layers disposed over the substrate, a passivation layer disposed over the one or more wiring layers, a first conductive layer disposed over the passivation layer, a second conductive layer disposed over the first conductive layer, an isolation structure formed in the first and second conductive layers to isolate a part of the first and second conductive layers, and a first metal pad disposed over the isolation structure and the part of the first and second conductive layers. In one or more of the foregoing or following embodiments, the semiconductor device further includes a second metal pad disposed over the second conductive layer and electrically isolated from the first metal pad.

Abstract: A method includes forming an interconnect structure over a semiconductor substrate. The interconnect structure includes a plurality of dielectric layers, and the interconnect structure and the semiconductor substrate are in a wafer. A plurality of metal pads are formed over the interconnect structure. A plurality of through-holes are formed to penetrate through the wafer. The plurality of through-holes include top portions penetrating through the interconnect structure, and middle portions underlying and joining to the top portions. The middle portions are wider than respective ones of the top portions. A metal layer is formed to electrically connect to the plurality of metal pads. The metal layer extends into the top portions of the plurality of through-holes.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes at least one substrate and an interconnection structure. The at least one substrate has a cavity partially defined by an inner sidewall of the at least one substrate and a channel disposed at a bottom of the at least one substrate. The channel laterally penetrates through the at least one substrate. The interconnections structure is disposed over the substrate, and the interconnection structure has a through hole penetrating through the interconnection structure. The through hole, the cavity and the channel are in spatial communication with each other.

Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.

Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.

Abstract: A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.