Patents by Inventor Fu Wei

Fu Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387281
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 30, 2023
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
  • Patent number: 11824109
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
  • Publication number: 20230369449
    Abstract: The transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chen-Ju Yu, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 11804538
    Abstract: A method of forming a high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chen-Ju Yu, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 11786217
    Abstract: The invention provides an intra-needle ultrasound system and its method of use for analysis, tracking, and display of pleura in millimeter-scale resolution. This method includes the following steps: Assembling the puncture needle and intra-needle ultrasound transducer, which can generate and receive ultrasound waves at the needle tip. To transform the axial ultrasonic signal into a figure, that can help to identify different anatomic structures according to the corresponding feature of ultrasonic RF (Radio Frequency) signal, and to set the region of interest according to corresponding RF feature of amplitude and depth. This invention can indicate the distance between the ultrasound needle tip and pleura in a real-time fashion, and to identify the best position for anesthetic injection in the paravertebral block (PVB) and the intercostals nerve block (ICNB). The system can also help to avoid damage to the pleura and lung during the nerve block procedure.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: October 17, 2023
    Assignees: NATIONAL YANG MING CHIAO TUNG UNIVERSITY, TAIPEI VETERANS GENERAL HOSPITAL
    Inventors: Huihua Chiang, Chien-Kun Ting, Shu-Wei Liao, Fu-Wei Su, Ching-Fang Yang, Chia-Wei Yang
  • Patent number: 11769716
    Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes at least one substrate and an interconnection structure. The at least one substrate has a cavity partially defined by an inner sidewall of the at least one substrate and a channel disposed at a bottom of the at least one substrate. The channel laterally penetrates through the at least one substrate. The interconnections structure is disposed over the substrate, and the interconnection structure has a through hole penetrating through the interconnection structure. The through hole, the cavity and the channel are in spatial communication with each other.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sheng Lin, Cheng-Lung Yang, Chin-Yu Ku, Ming-Da Cheng, Wen-Hsiung Lu, Tang-Wei Huang, Fu Wei Liu
  • Publication number: 20230299133
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A doped isolation region is disposed within the substrate and includes a horizontally extending segment and one or more vertically extending segments extending outward from the horizontally extending segment. The substrate includes a first sidewall and a second sidewall separated from the first sidewall a non-zero distance. The non-zero distance is directly over the one or more vertically extending segments.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan
  • Publication number: 20230246142
    Abstract: A package structure includes a circuit substrate, a light emitting diode array, a first encapsulant, and a sealant. The circuit substrate includes a top surface and a side surface of the circuit substrate. The light emitting diode array is disposed on the top surface of the circuit substrate. The first encapsulant is disposed above the circuit substrate. The first encapsulant includes a main portion and an extension portion, in which the main portion of the first encapsulant is disposed parallel to the top surface of the circuit substrate, and the extension portion of the first encapsulant extends to the side surface of the circuit substrate. The sealant is disposed below the extension portion of the first encapsulant, and the sealant contacts the first encapsulant and the circuit substrate. The first encapsulant and the sealant together form a coplanar surface.
    Type: Application
    Filed: December 7, 2022
    Publication date: August 3, 2023
    Inventors: Fu-Wei CHAN, Kuan-Hsun CHEN, Yi-Hsin LIN
  • Patent number: 11705486
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first III-V semiconductor material over a substrate and a second III-V semiconductor material over the first III-V semiconductor material. The second III-V semiconductor material is a different material than the first III-V semiconductor material. A doped region has a horizontally extending segment and one or more vertically extending segments protruding vertically outward from the horizontally extending segment. The horizontally extending segment is arranged below the first III-V semiconductor material.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan
  • Publication number: 20230187417
    Abstract: A display panel includes a substrate, light-emitting diodes, and a cured opaque encapsulant layer. The light-emitting diodes are disposed on a first surface of the substrate. The cured opaque encapsulant layer is disposed on the first surface and a side surface of the substrate, and surrounds the light emitting diodes. A second surface of the cured opaque encapsulant layer facing away from the substrate is a rough surface.
    Type: Application
    Filed: April 1, 2022
    Publication date: June 15, 2023
    Applicant: Au Optronics Corporation
    Inventors: Fu-Wei Chan, Kuan-Hsun Chen, Yi-Yueh Hsu
  • Publication number: 20230063096
    Abstract: A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Li Yang, Wen-Hsiung Lu, Jhao-Yi Wang, Fu Wei Liu, Chin-Yu Ku
  • Publication number: 20230060982
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a chip structure including a substrate and a wiring structure over a first surface of the substrate. The method includes removing a first portion of the wiring structure adjacent to the hole to widen a second portion of the hole in the wiring structure. The second portion has a first width increasing in a first direction away from the substrate. The method includes forming a first seed layer over the wiring structure and in the hole. The method includes thinning the substrate from a second surface of the substrate until the first seed layer in the hole is exposed. The method includes forming a second seed layer over the second surface of the substrate and the first seed layer in the hole.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Li YANG, Wen-Hsiung LU, Lung-Kai MAO, Fu-Wei LIU, Mirng-Ji LII
  • Publication number: 20230038731
    Abstract: A covering film (100) includes a first covering layer (10), a first adhesive layer (20), and a thermal conductive layer (30) sandwiched between the first covering layer (10) and the first adhesive layer (20). A thermal conductivity of the thermal conductive layer (30) is K1, K1=3˜65 W/m.K. A thermal conductivity of the first covering layer (10) is K2, K2=0.02˜3.0 W/m.K. A thermal conductivity of the first adhesive layer (20) is K3, K3=0.02˜1.0 W/m.K. A circuit board and its manufacturing method are also provided.
    Type: Application
    Filed: March 27, 2020
    Publication date: February 9, 2023
    Inventors: HSIAO-TING HSU, MING-JAAN HO, KATSUMI FUJIWARA, FU-YUN SHEN, FU-WEI ZHONG
  • Patent number: 11522066
    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Patent number: 11522077
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
  • Publication number: 20220359738
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
  • Publication number: 20220359295
    Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: MAN-HO KWAN, FU-WEI YAO, RU-YI SU, CHUN LIN TSAI, ALEXANDER KALNITSKY
  • Publication number: 20220310492
    Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes at least one substrate and an interconnection structure. The at least one substrate has a cavity partially defined by an inner sidewall of the at least one substrate and a channel disposed at a bottom of the at least one substrate. The channel laterally penetrates through the at least one substrate. The interconnections structure is disposed over the substrate, and the interconnection structure has a through hole penetrating through the interconnection structure. The through hole, the cavity and the channel are in spatial communication with each other.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sheng Lin, Cheng-Lung Yang, Chin-Yu Ku, Ming-Da Cheng, Wen-Hsiung Lu, Tang-Wei Huang, Fu Wei Liu
  • Publication number: 20220285540
    Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
  • Patent number: 11430702
    Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Ru-Yi Su, Chun Lin Tsai, Alexander Kalnitsky