Patents by Inventor Fu Wei

Fu Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200204970
    Abstract: A wireless access method for a communication system is provided. The wireless access method is adapted to a base station, and includes the following steps. A first control information is transmitted through a first frequency band. A second control information is transmitted through a second frequency band. The time difference between the transmission time points of the first control information and the second control information is less than a slot time, and the first frequency band is different from the second frequency band.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 25, 2020
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hung-Fu WEI, Jing-Shiun LIN, Chiu-Ping WU, Jen-Yuan HSU
  • Publication number: 20200098889
    Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Publication number: 20200083324
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a channel layer disposed over a substrate and including a first material. An active layer is over the channel layer and includes a second material different than the first material. An isolation structure has a horizontally extending segment that is below the channel layer and one or more vertically extending segments that are directly over the horizontally extending segment. One or more contacts extend through the channel layer and the active layer to contact the one or more vertically extending segments.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan
  • Patent number: 10541743
    Abstract: A communication system and an operating method thereof are provided. The communication system includes at least one user equipment, at least one remote radio head (RRH), a measuring unit, a set determining unit and an antenna selecting unit. The RRH is electrically connected to a plurality of antennas. The measuring unit is for controlling a measurement of a signal strength of the at least one user equipment. The set determining unit is used for selecting one of a plurality of antenna configuration sets according to the signal strength for the at least one user equipment. Each of the antenna configuration sets includes a plurality of antenna configurations. Each of the antenna configurations is composed of P of a plurality of antennas. The antenna selecting unit is used for allocating one of the antenna configurations from the antenna configuration set which is selected for the at least one user equipment.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 21, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Hao Fang, Jen-Yuan Hsu, Hung-Fu Wei, Chien-Yu Kao
  • Patent number: 10522618
    Abstract: An isolation structure for active devices is provided. In some embodiments, the isolation structure is used in a transistor. The transistor includes a substrate having a first doping type. The transistor also includes a channel layer positioned over the substrate and comprising a first section and a second section. The transistor further includes an active layer positioned over the channel layer. The isolation structure includes a horizontal segment, a first vertical segment, and a second vertical segment. The horizontal segment is arranged below the second section of the channel layer and continuously extends between the first vertical segment and the second vertical segment. The isolation structure has a second doping type that is different than the first doping type.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan
  • Patent number: 10522630
    Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chih-Wen Hsiung, King-Yuen Wong
  • Patent number: 10522647
    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer. Source and drain regions are arranged over the second III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Publication number: 20190287857
    Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Inventors: MAN-HO KWAN, FU-WEI YAO, RU-YI SU, CHUN LIN TSAI, ALEXANDER KALNITSKY
  • Patent number: 10411681
    Abstract: A device includes a first transistor having a first source terminal, a first drain terminal, and a first gate terminal; and a second transistor having a second source terminal, a second drain terminal, and a second gate terminal. The second source terminal is coupled to the first gate terminal and the first source terminal is coupled to the second gate terminal. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage different from the first threshold voltage.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Ru-Yi Su, King-Yuen Wong
  • Patent number: 10395056
    Abstract: A method, system, and computer product for protecting personal privacy of one or more persons in a photo are provided. The method comprises receiving a photo including a face of at least one person, performing face recognition on the at least one person in the photo, determining a cross-relationship value between another person and the at least one person, based on a degree of closeness between said another person and the at least one person, and determining whether to show said another person the face of the at least one person in the photo, based on the cross-relationship value.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jia Tao Li, Jun Hui Ma, Hong Fu Wei, Zhen Ling Yu
  • Publication number: 20190252510
    Abstract: A high electron mobility transistor (HEMT) includes a first compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second compound layer between the salicide source feature and the salicide drain feature.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Fu-Wei YAO, Chen-Ju YU, King-Yuen WONG, Chun-Wei HSU, Jiun-Lei Jerry YU, Fu-Chih YANG, Chun Lin TSAI
  • Publication number: 20190245046
    Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Inventors: Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chih-Wen Hsiung, King-Yuen Wong
  • Publication number: 20190237539
    Abstract: An isolation structure for active devices is provided. In some embodiments, the isolation structure is used in a transistor. The transistore includes a substrate having a first doping type. The transistor also includes a channel layer positioned over the substrate and comprising a first section and a second section. The transistor further includes an active layer positioned over the channel layer. The isolation structure includes a horizontal segment, a first vertical segment, and a second vertical segment. The horizontal segment is arranged below the second section of the channel layer and continuously extends between the first vertical segment and the second vertical segment. The isolation structure has a second doping type that is different than the first doping type.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan
  • Publication number: 20190190584
    Abstract: A communication system and an operating method thereof are provided. The communication system includes at least one user equipment, at least one remote radio head (RRH), a measuring unit, a set determining unit and an antenna selecting unit. The RRH is electrically connected to a plurality of antennas. The measuring unit is for controlling a measurement of a signal strength of the at least one user equipment. The set determining unit is used for selecting one of a plurality of antenna configuration sets according to the signal strength for the at least one user equipment. Each of the antenna configuration sets includes a plurality of antenna configurations. Each of the antenna configurations is composed of P of a plurality of antennas. The antenna selecting unit is used for allocating one of the antenna configurations from the antenna configuration set which is selected for the at least one user equipment.
    Type: Application
    Filed: December 28, 2017
    Publication date: June 20, 2019
    Inventors: Shih-Hao FANG, Jen-Yuan HSU, Hung-Fu WEI, Chien-Yu KAO
  • Publication number: 20190190585
    Abstract: A communication system, a coordinator and a controlling method thereof are provided. The embodiment of the communication system is used for one or more user equipments. The controlling method includes the following steps. A measurement of a plurality of antenna configurations corresponding to the one or more user equipments is controlled to obtain a plurality of performance values. The performance values of the antenna configurations corresponding to the one or more user equipments are recorded. An embodiment of the communication system includes a plurality of Remote Radio Heads, each of which is electronically connected to a plurality of antennas.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 20, 2019
    Inventors: Shih-Hao FANG, Jen-Yuan HSU, Hung-Fu WEI, Chien-Yu KAO
  • Patent number: 10319644
    Abstract: In some embodiments, a semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: June 11, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Ru-Yi Su, Chun Lin Tsai, Alexander Kalnitsky
  • Publication number: 20190142180
    Abstract: An inflation identification connector and an air mattress system having the same is provided. The inflation identification connector is insertable into a connection seat of a gas delivery host. The connection seat has a light detection component coupled to a controller disposed in the gas delivery host. The inflation identification connector includes a body and an identification structure. The detection result of the light detection component depends on the identification structure and thus is conducive to identification. Upon its insertion into the connection seat, the inflation identification connector is identified by the gas delivery host, enhancing ease of use and protecting manual operation against mistakes. The gas delivery host is not only applicable to different types of air mattresses but also conducive to streamlined management of the air mattress system and reduction of management costs and risks.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 16, 2019
    Inventors: DAVID HUANG, WEN-BIN SHEN, JU-CHIEN CHENG, MING-HENG HSIEH, FU-WEI CHEN, CHIH-KUANG CHANG, YI-LING LIU, SHENG-WEI LIN, CHUNG-YI LIN
  • Patent number: 10283599
    Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chih-Wen Hsiung, King-Yuen Wong
  • Publication number: 20190131427
    Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.
    Type: Application
    Filed: December 13, 2018
    Publication date: May 2, 2019
    Inventors: Chen-Ju YU, Chih-Wen HSIUNG, Fu-Wei YAO, Chun-Wei HSU, King-Yuen WONG, Jiun-Lei Jerry YU, Fu-Chih YANG
  • Patent number: 10276657
    Abstract: An isolation structure for active devices is provided. In some embodiments, the isolation structure is used in a transistor. The transistore includes a substrate having a first doping type. The transistor also includes a channel layer positioned over the substrate and comprising a first section and a second section. The transistor further includes an active layer positioned over the channel layer. The isolation structure includes a horizontal segment, a first vertical segment, and a second vertical segment. The horizontal segment is arranged below the second section of the channel layer and continuously extends between the first vertical segment and the second vertical segment. The isolation structure has a second doping type that is different than the first doping type.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan