Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.

Abstract: An isolation structure for active devices is provided. In some embodiments, the isolation structure is used in a transistor. The transistore includes a substrate having a first doping type. The transistor also includes a channel layer positioned over the substrate and comprising a first section and a second section. The transistor further includes an active layer positioned over the channel layer. The isolation structure includes a horizontal segment, a first vertical segment, and a second vertical segment. The horizontal segment is arranged below the second section of the channel layer and continuously extends between the first vertical segment and the second vertical segment. The isolation structure has a second doping type that is different than the first doping type.

Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

Abstract: A printed circuit board used as a voice coil includes N board units stacked over one another, each board unit having a first electrically connecting region and a second electrically connecting region, all of the first electrically connecting regions being stacked over one another, all of the second electrically connecting regions being stacked over one another, each board unit having a first circuit structure, a base, and a second circuit structure arranged from top to bottom, in each two adjacent board units, the first electrically connecting region of the second circuit structure of an upper board unit being electrically connected in series with the first electrically connecting region of the first circuit structure of a lower board unit, in each board unit, the first circuit structure being electrically connected in series with the second circuit structure in the second electrically connecting region.

Abstract: A method, system, and computer product for protecting personal privacy of one or more persons in a photo are provided. The method comprises receiving a photo including a face of at least one person, performing face recognition on the at least one person in the photo, determining a cross-relationship value between another person and the at least one person, based on a degree of closeness between said another person and the at least one person, and determining whether to show said another person the face of the at least one person in the photo, based on the cross-relationship value.

Abstract: The present disclosure relates to a flexible circuit board. The flexible circuit board includes a first conductive trace substrate and a third conductive layer, a second conductive post and a third conductive post. The first conductive trace substrate includes a first insulating layer, a first conductive layer and a second conductive layer formed two opposite surfaces of the first insulating layer. The first conductive layer includes a first signal line, the second conductive layer includes a second signal line, and the first signal line is parallel connected with the second signal line.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is over the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located at an interface of the first III-V compound layer and the second III-V compound layer. Slanted field plates are in an opening in a dielectric layer over the second III-V compound layer; the gate electrode is disposed in the opening.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer. Source and drain regions are arranged over the second III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: A printed circuit board used as a voice coil includes N board units stacked over one another, each board unit having a first electrically connecting region and a second electrically connecting region, all of the first electrically connecting regions being stacked over one another, all of the second electrically connecting regions being stacked over one another, each board unit having a first circuit structure, a base, and a second circuit structure arranged from top to bottom, in each two adjacent board units, the first electrically connecting region of the second circuit structure of an upper board unit being electrically connected in series with the first electrically connecting region of the first circuit structure of a lower board unit, in each board unit, the first circuit structure being electrically connected in series with the second circuit structure in the second electrically connecting region.

Abstract: A circuit structure includes a substrate, a III-V semiconductor compound over the substrate, a AlxGa(1-X)N (AlGaN) layer over the III-V semiconductor compound, a gate over the AlGaN layer, a passivation film over the gate and over a portion of the AlGaN layer, a source structure, and a drain structure on an opposite side of the gate from the source structure, wherein X ranges from 0.1 to 1. The source structure has a source contact portion and an overhead portion. The overhead portion is over at least a portion of the passivation film between the source contact portion and the gate. A distance between the source contact portion and the gate is less than a distance between the gate and the drain structure.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

Abstract: An annotation retrieval module may be configured to retrieve annotations added to sample data, the annotations having been added according to an annotation rule. An analysis tool may be configured to create a logical schema and a configuration file from the retrieved annotations, according to the annotation rule. The logic schema may represent a tree structure containing one or more data elements corresponding to the sample data, and the configuration file may define one or more operations for adding DFDL annotations into the logic schema. A DFDL schema generator may be configured to generate a DFDL schema for the sample data according to the logic schema and the configuration file.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: A method of making a circuit structure includes growing a bulk layer over a substrate, and growing a donor-supply layer over the bulk layer. The method further includes depositing a doped layer over the donor-supply layer, and patterning the doped layer to form a plurality of islands. The method further includes forming a gate structure over the donor-supply layer, wherein the gate structure is partially over a largest island of the plurality of islands. The method further includes forming a drain over the donor-supply layer, wherein at least one island of the plurality of islands is between the gate structure and the drain.

Abstract: A printed circuit board includes a first printed circuit substrate and a second printed circuit substrate. The first printed circuit substrate includes a substrate layer and a first conductive circuit layer. The first conductive circuit layer is formed on the substrate layer. The substrate layer includes at least two first grooves. The first conductive circuit layer includes at least one signal wire. The first grooves are defined in both sides of the signal wire. The second printed circuit substrate is formed on the first printed circuit substrate. The second circuit substrate includes a third copper layer. A second groove is defined in the third copper layer. The first grooves are opposite to the second groove. The first grooves and the second groove form a space.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.

Abstract: A device includes a first transistor having a first source terminal, a first drain terminal, and a first gate terminal; and a second transistor having a second source terminal, a second drain terminal, and a second gate terminal. The second source terminal is coupled to the first gate terminal and the first source terminal is coupled to the second gate terminal. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage different from the first threshold voltage.

Abstract: A semiconductor device includes a first transistor and a clamping circuit. The first transistor is arranged to generate an output signal according to a control signal. The clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level.