Patents by Inventor Fu Wei

Fu Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11404557
    Abstract: A method of forming a high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chen-Ju Yu, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 11349023
    Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
  • Publication number: 20210376135
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
  • Publication number: 20210280689
    Abstract: A method of forming a high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 9, 2021
    Inventors: Chun-Wei HSU, Jiun-Lei Jerry YU, Fu-Wei YAO, Chen-Ju YU, Fu-Chih YANG, Chun Lin TSAI
  • Patent number: 11005548
    Abstract: A multi-antenna system includes: a server; a first antenna group, provided on a base station and including multiple first antennas including a first representative antenna and a first non-representative antenna, the base station performing intra-group channel estimation to obtain and transmit to the server multiple first inner channel estimation coefficients between the first representative antenna and the first non-representative antenna, and serving a user device; and a reference device, communicating with the server and the first antennas, performing channel estimation between the reference device and the first representative antenna to obtain and transmit to the server multiple first outer channel estimation coefficients between the reference device and the first representative antenna. The server calculates a precoding matrix according to the first inner and first outer channel estimation coefficients, and the base station performs data transmission with the user device according to the precoding matrix.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: May 11, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jia-Ming Chen, Hung-Fu Wei, Jyun-Wei Lai, Jen-Yuan Hsu
  • Publication number: 20210119011
    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.
    Type: Application
    Filed: December 8, 2020
    Publication date: April 22, 2021
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Publication number: 20210098615
    Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
  • Publication number: 20210043726
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first III-V semiconductor material over a substrate and a second III-V semiconductor material over the first III-V semiconductor material. The second III-V semiconductor material is a different material than the first III-V semiconductor material. A doped region has a horizontally extending segment and one or more vertically extending segments protruding vertically outward from the horizontally extending segment. The horizontally extending segment is arranged below the first III-V semiconductor material.
    Type: Application
    Filed: October 27, 2020
    Publication date: February 11, 2021
    Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan
  • Patent number: 10911919
    Abstract: A wireless access method for a communication system is provided. The wireless access method is adapted to a base station, and includes the following steps. A first control information is transmitted through a first frequency band. A second control information is transmitted through a second frequency band. The time difference between the transmission time points of the first control information and the second control information is less than a slot time, and the first frequency band is different from the second frequency band.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: February 2, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hung-Fu Wei, Jing-Shiun Lin, Chiu-Ping Wu, Jen-Yuan Hsu
  • Patent number: 10868135
    Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Ju Yu, Chih-Wen Hsiung, Fu-Wei Yao, Chun-Wei Hsu, King-Yuen Wong, Jiun-Lei Jerry Yu, Fu-Chih Yang
  • Patent number: 10868136
    Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Patent number: 10868134
    Abstract: A channel layer is grown over a substrate, and an active layer is grown over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A dielectric layer is deposited over the active layer, and the dielectric layer is patterned to expose a portion of the active layer. A metal diffusion barrier is formed over the exposed portion of the active layer, and a gate is deposited over the metal diffusion barrier.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: King-Yuen Wong, Po-Chih Chen, Chen-Ju Yu, Fu-Chih Yang, Jiun-Lei Jerry Yu, Fu-Wei Yao, Ru-Yi Su, Yu-Syuan Lin
  • Patent number: 10854711
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a channel layer disposed over a substrate and including a first material. An active layer is over the channel layer and includes a second material different than the first material. An isolation structure has a horizontally extending segment that is below the channel layer and one or more vertically extending segments that are directly over the horizontally extending segment. One or more contacts extend through the channel layer and the active layer to contact the one or more vertically extending segments.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan
  • Publication number: 20200373408
    Abstract: A method of forming a high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Chun-Wei HSU, Jiun-Lei Jerry YU, Fu-Wei YAO, Chen-Ju YU, Fu-Chih YANG, Chun Lin TSAI
  • Publication number: 20200366356
    Abstract: A multi-antenna system includes: a server; a first antenna group, provided on a base station and including multiple first antennas including a first representative antenna and a first non-representative antenna, the base station performing intra-group channel estimation to obtain and transmit to the server multiple first inner channel estimation coefficients between the first representative antenna and the first non-representative antenna, and serving a user device; and a reference device, communicating with the server and the first antennas, performing channel estimation between the reference device and the first representative antenna to obtain and transmit to the server multiple first outer channel estimation coefficients between the reference device and the first representative antenna. The server calculates a precoding matrix according to the first inner and first outer channel estimation coefficients, and the base station performs data transmission with the user device according to the precoding matrix.
    Type: Application
    Filed: September 9, 2019
    Publication date: November 19, 2020
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jia-Ming Chen, Hung-Fu Wei, Jyun-Wei Lai, Jen-Yuan Hsu
  • Patent number: 10790375
    Abstract: A high electron mobility transistor (HEMT) includes a first compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second compound layer between the salicide source feature and the salicide drain feature.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Wei Yao, Chen-Ju Yu, King-Yuen Wong, Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 10741665
    Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chen-Ju Yu, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 10709255
    Abstract: An inflation identification connector and an air mattress system having the same is provided. The inflation identification connector is insertable into a connection seat of a gas delivery host. The connection seat has a light detection component coupled to a controller disposed in the gas delivery host. The inflation identification connector includes a body and an identification structure. The detection result of the light detection component depends on the identification structure and thus is conducive to identification. Upon its insertion into the connection seat, the inflation identification connector is identified by the gas delivery host, enhancing ease of use and protecting manual operation against mistakes. The gas delivery host is not only applicable to different types of air mattresses but also conducive to streamlined management of the air mattress system and reduction of management costs and risks.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 14, 2020
    Assignee: APEX MEDICAL CORP.
    Inventors: David Huang, Wen-Bin Shen, Ju-Chien Cheng, Ming-Heng Hsieh, Fu-Wei Chen, Chih-Kuang Chang, Yi-Ling Liu, Sheng-Wei Lin, Chung-Yi Lin
  • Publication number: 20200214678
    Abstract: The invention provides an intra-needle ultrasound system and its method of use for analysis, tracking, and display of pleura in millimeter-scale resolution. This method includes the following steps: Assembling the puncture needle and intra-needle ultrasound transducer, which can generate and receive ultrasound waves at the needle tip. To transform the axial ultrasonic signal into a figure, that can help to identify different anatomic structures according to the corresponding feature of ultrasonic RF (Radio Frequency) signal, and to set the region of interest according to corresponding RF feature of amplitude and depth. This invention can indicate the distance between the ultrasound needle tip and pleura in a real-time fashion, and to identify the best position for anesthetic injection in the paravertebral block (PVB) and the intercostals nerve block (ICNB). The system can also help to avoid damage to the pleura and lung during the nerve block procedure.
    Type: Application
    Filed: November 29, 2019
    Publication date: July 9, 2020
    Inventors: Huihua CHIANG, Chien-Kun TING, Shu-Wei LIAO, Fu-Wei SU, Ching-Fang YANG, Chia-Wei YANG
  • Publication number: 20200204414
    Abstract: A communication device and a transmitting and receiving method thereof. The communication device configured to transmit a first signal includes a code block (CB) segmentation unit, a plurality of first processing units, and a first resource mapping module. The CB segmentation unit is configured to divide at least one first transport block corresponding to the first signal into a plurality of first code blocks. Each of the first code blocks corresponds to one of the first processing units. The first processing units encode the first code blocks to obtain a plurality of first symbols. The resource mapping module performs resource mapping of the first symbols to obtain a first resource block.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hung-Fu WEI, Jing-Shiun LIN, Chiu-Ping WU, Jen-Yuan HSU