Patents by Inventor Fu Wei

Fu Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Plasma protection diode for a HEMT device
    Patent number: 9871030
    Abstract: A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: King-Yuen Wong, Chun-Wei Hsu, Chen-Ju Yu, Fu-Wei Yao, Jiun-Lei Jerry Yu, Fu-Chih Yang, Po-Chih Chen
  • High Electron Mobility Transistor Structure and Method of Making the Same
    Publication number: 20170338316
    Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.
    Type: Application
    Filed: August 7, 2017
    Publication date: November 23, 2017
    Inventors: Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chih-Wen Hsiung, King-Yuen Wong
  • Method of Forming a High Electron Mobility Transistor
    Publication number: 20170317184
    Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.
    Type: Application
    Filed: July 10, 2017
    Publication date: November 2, 2017
    Inventors: Chun-Wei Hsu, Jiun-Lei Jerry YU, Fu-Wei YAO, Chen-Ju YU, Fu-Chih YANG, Chun Lin TSAI
  • Method of forming a high electron mobility transistor
    Patent number: 9793371
    Abstract: A method of forming a high electron mobility transistor (HEMT) includes forming a second III-V compound layer on a first III-V compound layer, forming a source feature and a drain feature on the second III-v compound layer, depositing a p-type layer on a portion of the second III-V compound layer between the source feature and the drain feature, and forming a gate electrode on the p-type layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 17, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Wei Hsu, Po-Chih Chen, King-Yuen Wong, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chen-Ju Yu
  • SIDEWALL PASSIVATION FOR HEMT DEVICES
    Publication number: 20170271473
    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • PRINTED CIRCUIT BOARD
    Publication number: 20170265295
    Abstract: A printed circuit board includes a first printed circuit substrate and a second printed circuit substrate. The first printed circuit substrate includes a substrate layer and a first conductive circuit layer. The first conductive circuit layer is formed on the substrate layer. The substrate layer includes at least two first grooves. The first conductive circuit layer includes at least one signal wire. The first grooves are defined in both sides of the signal wire. The second printed circuit substrate is formed on the first printed circuit substrate. The second circuit substrate includes a third copper layer. A second groove is defined in the third copper layer. The first grooves are opposite to the second groove. The first grooves and the second groove form a space.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Inventors: MING-JAAN HO, XIAN-QIN HU, YI-QIANG ZHUANG, FU-WEI ZHONG
  • Rectifier structures with low leakage
    Patent number: 9755045
    Abstract: An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Chen-Ju Yu, Jiun-Lei Jerry Yu, Po-Chih Chen, Fu-Wei Yao, Fu-Chih Yang
  • Semiconductor structure and method of forming the same
    Patent number: 9748372
    Abstract: A method of forming a semiconductor structure includes growing a second III-V compound layer over a first III-V compound layer, wherein the second III-V compound layer has a different band gap from the first III-V compound layer. The method further includes forming a source feature and a drain feature over the second III-V compound layer. The method further includes forming a gate dielectric layer over the second III-V compound layer, the source feature and the drain feature. The method further includes implanting at least one fluorine-containing compound into a portion of the gate dielectric layer. The method further includes forming a gate electrode over the portion of the gate dielectric layer.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: August 29, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: King-Yuen Wong, Chen-Ju Yu, Fu-Wei Yao, Chun-Wei Hsu, Jiun-Lei Jerry Yu, Chih-Wen Hsiung, Fu-Chih Yang
  • High electron mobility transistor structure
    Patent number: 9728613
    Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chih-Wen Hsiung, King-Yuen Wong
  • Method for manufacturing printed circuit board
    Patent number: 9706640
    Abstract: A printed circuit board includes a first printed circuit substrate and a second printed circuit substrate. The first printed circuit substrate includes a substrate layer and a first conductive circuit layer. The first conductive circuit layer is formed on the substrate layer. The substrate layer includes at least two first grooves. The first conductive circuit layer includes at least one signal wire. The first grooves are defined in both sides of the signal wire. The second printed circuit substrate is formed on the first printed circuit substrate. The second circuit substrate includes a third copper layer. A second groove is defined in the third copper layer. The first grooves are opposite to the second groove. The first grooves and the second groove form a space. The signal wire is surrounded by air in the space. A method for manufacturing the printed circuit board is also provided.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 11, 2017
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., HongQiSheng Precision Electronics (QinHuangDao) Co.,Ltd., GARLIDA TECHNOLOGY CO., LTD.
    Inventors: Ming-Jaan Ho, Xian-Qin Hu, Yi-Qiang Zhuang, Fu-Wei Zhong
  • Method of forming a high electron mobility transistor
    Patent number: 9704968
    Abstract: A method of forming a high electron mobility transistor (HEMT) that includes epitaxially growing a second III-V compound layer on a first III-V compound layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are formed on the second III-V compound layer. A p-type layer is deposited on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is formed on a portion of the p-type layer.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chen-Ju Yu, Fu-Chih Yang, Chun Lin Tsai
  • METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
    Publication number: 20170186647
    Abstract: In some embodiments, a semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 29, 2017
    Inventors: MAN-HO KWAN, FU-WEI YAO, RU-YI SU, CHUN LIN TSAI, ALEXANDER KALNITSKY
  • SEMICONDUCTOR DEVICE AND CIRCUIT PROTECTING METHOD
    Publication number: 20170179935
    Abstract: A semiconductor device includes a first transistor and a clamping circuit. The first transistor is arranged to generate an output signal according to a control signal. The clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level.
    Type: Application
    Filed: September 8, 2016
    Publication date: June 22, 2017
    Inventors: MAN-HO KWAN, FU-WEI YAO, RU-YI SU, KING-YUEN WONG
  • Sidewall passivation for HEMT devices
    Patent number: 9685525
    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE
    Publication number: 20170170295
    Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 15, 2017
    Inventors: Chen-Ju YU, Chih-Wen HSIUNG, Fu-Wei YAO, Chun-Wei HSU, King-Yuen WONG, Jiun-Lei Jerry YU, Fu-Chih YANG
  • Sun control textile with high transmittance and manufacturing method thereof
    Patent number: 9677204
    Abstract: A sun control textile with high transmittance and a manufacturing method thereof. In the manufacturing method of the sun control textile, a high-performance sun control film is processed into slender filaments. The slender filaments are woven and assembled with other yarns by a weaving device to together form a sun control textile. The different connection manners of the sun control film yarns lead to different visible light transmittance and sun control effect of the sun control textile, whereby an excellent sun control textile with high transmittance can be achieved.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: June 13, 2017
    Assignee: Rainbow Package Industrial Co., Ltd.
    Inventor: Tsan Fu Wei
  • CIRCUIT STRUCTURE, TRANSISTOR AND SEMICONDUCTOR DEVICE
    Publication number: 20170133484
    Abstract: A circuit structure includes a substrate, a III-V semiconductor compound over the substrate, a AlxGa(1-x)N (AlGaN) layer over the III-V semiconductor compound, a gate over the AlGaN layer, a passivation film over the gate and over a portion of the AlGaN layer, a source structure, and a drain structure on an opposite side of the gate from the source structure, wherein X ranges from 0.1 to 1. The source structure has a source contact portion and an overhead portion. The overhead portion is over at least a portion of the passivation film between the source contact portion and the gate. A distance between the source contact portion and the gate is less than a distance between the gate and the drain structure.
    Type: Application
    Filed: January 23, 2017
    Publication date: May 11, 2017
    Inventors: Jiun-Lei Jerry YU, Fu-Wei YAO, Chen-Ju YU, Chun-Wei HSU, King-Yuen WONG
  • SUN CONTROL TEXTILE WITH HIGH TRANSMITTANCE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170121867
    Abstract: A sun control textile with high transmittance and a manufacturing method thereof. In the manufacturing method of the sun control textile, a high-performance sun control film is processed into slender filaments. The slender filaments are woven and assembled with other yarns by a weaving device to together form a sun control textile. The different connection manners of the sun control film yarns lead to different visible light transmittance and sun control effect of the sun control textile, whereby an excellent sun control textile with high transmittance can be achieved.
    Type: Application
    Filed: March 1, 2016
    Publication date: May 4, 2017
    Inventor: TSAN FU WEI
  • HYBRID SEMICONDUCTOR STRUCTURE ON A COMMON SUBSTRATE
    Publication number: 20170125296
    Abstract: A semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: MAN-HO KWAN, FU-WEI YAO, RU-YI SU, CHUN LIN TSAI, ALEXANDER KALNITSKY
  • Hybrid semiconductor structure on a common substrate
    Patent number: 9627275
    Abstract: A semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Man-Ho Kwan, Fu-Wei Yao, Ru-Yi Su, Chun Lin Tsai, Alexander Kalnitsky