Abstract: Disclosed are small molecule inhibitors of ?v?6 integrin, and methods of using them to treat a number of diseases and conditions.

Abstract: Disclosed are small molecule inhibitors of ?v?6 integrin, and methods of using them to treat a number of diseases and conditions.

Abstract: A method includes placing a photomask having a contamination on a surface thereof in a plasma processing chamber. The contaminated photomask is plasma processed in the plasma processing chamber to remove the contamination from the surface. The plasma includes oxygen plasma or hydrogen plasma.

Abstract: Disclosed are small molecule inhibitors of ?v?6 integrin, and methods of using them to treat a number of diseases and conditions.

Abstract: Disclosed are small molecule inhibitors of ?v?6 integrin, and methods of using them to treat a number of diseases and conditions.

Abstract: An impeller is provided, including a metal housing, a shaft, and a plastic member. The metal housing has a shaft mounting hole. The inner surface of the shaft mounting hole includes three or more contact points, and the contact points are closer to the shaft than other portions of the inner surface of the shaft mounting hole. The shaft passes through the shaft mounting hole and is affixed by the contact points. The metal housing divides the shaft into an upper section, a middle section, and a lower section. The plastic member passes through the shaft mounting hole and is in contact with the middle section.

Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.

Abstract: A heat dissipation assembly is disclosed and includes a frame and a fan. The frame includes a heat conduction channel and an airflow intake. The heat conduction channel is communication with an exterior through airflow intake. The frame includes a first plane, a second plane and an inclined plane. The first plane is disposed adjacent to the airflow intake. The inclined plane is connected between the first plane and the second plane. The second plane includes an inlet. The heat conduction channel is in communication between the airflow intake and the inlet. A cross-section area of the heat conduction channel adjacent to the airflow intake is greater than that of the heat conduction channel adjacent to the inlet. The fan is spatially corresponding to the inlet, and assembled with the frame to form an outlet in communication with the airflow intake and the heat conduction channel through the inlet.

Abstract: A fan impeller includes a hub, a shaft, a metal housing and a plurality of blades. The outer periphery of the hub has a curved surface. The shaft is disposed in the hub and connected to the hub. The metal housing has an annular shape and is disposed in the hub. A magnetic ring is disposed at the inner side of the metal housing. The blades are disposed around the outer periphery of the hub. The blades are projected along an extension direction toward the shaft to define projection areas thereof, and the projection area of a top and a bottom of any one of the blades is partially overlapped with other two adjacent blades. A distance between an outer edge of each blade and a rotational axis of the fan decreases proximate the top of the blade and then increases towards the bottom of the blade.

Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.

Abstract: An impeller is provided, including a metal housing, a shaft, and a plastic member. The metal housing has a shaft mounting hole. The inner surface of the shaft mounting hole includes three or more contact points, and the contact points are closer to the shaft than other portions of the inner surface of the shaft mounting hole. The shaft passes through the shaft mounting hole and is affixed by the contact points. The metal housing divides the shaft into an upper section, a middle section, and a lower section. The plastic member passes through the shaft mounting hole and is in contact with the middle section.

Abstract: A light emitting diode (LED) package structure includes a first insulating layer, a first conductive pattern, a second insulating layer, a second conductive pattern, an LED element, and a solder material. The first conductive pattern has a first portion and a second portion, the first portion fills a through hole of the first insulating layer, and the second portion is disposed on the first insulating layer. The second insulating layer is disposed on the first insulating layer and covers the first conductive pattern. The second portion of the first conductive pattern is sandwiched between the first insulating layer and the second insulating layer. The second conductive pattern is disposed on the second insulating layer and is electrically connected to the first conductive pattern. The LED element is bonded to the second conductive pattern. The solder material is disposed on the first portion of the first conductive pattern.

Abstract: The disclosure relates to an asymmetrical double-outlet blower, including an upper case, a lower case and an impeller. The upper case includes an inlet. The lower case and the upper case are assembled to form a housing having an accommodation space, and form a first outlet and a second outlet. The accommodation space is in fluid communication with the first outlet, the second outlet and the inlet. The first outlet and the second outlet are disposed on a lateral periphery of the housing and face two opposite directions, respectively. An opening cross-sectional area of the first outlet is less than an opening cross-sectional area of the second outlet. The impeller is accommodated within the accommodation space of the housing, spatially corresponding to the inlet, and rotated around a rotation axis. An airflow is inhaled through the inlet and transported to the first outlet and the second outlet, respectively.

Abstract: A semiconductor device includes a substrate, a 2-D material layer, source/drain contacts, and a gate electrode. The 2-D material layer is over the substrate, the 2-D material layer includes source/drain regions and a channel region between the source/drain regions, in which the 2-D material layer is made of a transition metal dichalcogenide (TMD). The source/drain contacts are in contact with source/drain regions of the 2-D material layer, in which a binding energy of transition metal atoms at the channel region of the 2-D material layer is different from a binding energy of the transition metal atoms at the source/drain regions of the 2-D material layer. The gate electrode is over the substrate.

Abstract: Described herein is a multi-level power convertor and a method for a multi-level power convertor. The multi-level power convertor includes a DC port; an AC port; a first power converting unit, a second power converting unit, a coupling inductor, and an inductive filtering unit. The first power converting unit is coupled to the DC port and includes a first AC terminal adapted to provide a first plurality of voltage levels. The second power converting unit is coupled to the DC port and includes a second AC terminal adapted to provide a second plurality of voltage levels, where the second plurality of voltage levels are phase-shifted by 90 degrees with respect to the first plurality of voltage levels. The coupling inductor includes first and second windings with a same number of turns. The inductive filtering unit is arranged between the AC port and ends of the first and second windings.

Abstract: Disclosed are small molecule antagonists of ?4?7 integrin, and methods of using them to treat a number of specific diseases or conditions.

Abstract: A calibration device includes a main control unit, an interface conversion unit and an electronic load generation unit. The electronic load generation unit provides an electronic load, so that a USB control chip generates a constant load current. The USB control chip uses at least one preset conversion parameter to generate an analog-to-digital conversion value according to the constant load current. The main control unit generates a to-be-calibrated output current according to the analog-to-digital conversion value. The main control unit generates at least one calibrated conversion parameter according to the constant load current and the to-be-calibrated output current. The USB control chip uses the at least one calibrated conversion parameter to generate a calibrated analog-to-digital conversion value, so that an over current protection mechanism is accurately enabled.

Abstract: A method includes placing a photomask having a contamination on a surface thereof in a plasma processing chamber. The contaminated photomask is plasma processed in the plasma processing chamber to remove the contamination from the surface. The plasma includes oxygen plasma or hydrogen plasma.

Abstract: The product detection system includes a computing device, at least one power detection instrument and a product detection device. The product detection device includes a processing unit, plural USB-C transmission ports and plural detection connection ports. A product detection method includes following steps. Firstly, at least one USB-C under-test product is connected with the plural USB-C transmission ports, and the at least one power detection instrument is connected with the plural detection connection ports. Then, the USB-C transmission port is set as a first role or a second role. Then, the USB-C transmission port corresponding to the first role is cyclically operated at plural designated voltages under control of the processing unit, and the processing unit issues an output voltage to the USB-C transmission port corresponding to the second role. Then, an operation status of the USB-C under-test product is detected.