Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Abstract: A non-volatile memory device includes a first semiconductor body extending in a first direction and a second semiconductor body arranged side by side with the first semiconductor body. The second semiconductor body extends in the first direction. The device further includes a first electrode between the first semiconductor body and the second semiconductor body and extending in a second direction crossing the first direction, a first charge storage layer between the first electrode and the first semiconductor body, and a second charge storage layer between the first electrode and the second semiconductor body.

Abstract: According to one embodiment, a semiconductor memory device includes a first array extending in a first direction, a second array extending in the first direction, and a second electrode film. The second array is arranged with the first array in a second direction crossing the first direction. The second electrode film provided between the first array and the second array. The second electrode film extends in the first direction. Each of the first array and the second array include a first structure, a second structure arranged in the first direction, a fourth insulating film provided between the first structure and the second structure, and a third insulating film provided between the first structure and the second electrode film, provided also between the first structure and the fourth insulating film.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein and a control circuit that performs a writing operation on the memory cells. The writing operation performed by the control circuit includes a pre-programming verification operation to determine a threshold level of a memory cell in an erasure state, and a program operation in which a program voltage is selected from a plurality of program voltages on the basis of a determination result of the pre-programming verification operation.

Abstract: According to an embodiment, an operation method for a memory device which has a first memory element and a second memory element respectively provided on both sides of a semiconductor member includes applying a first potential on the second word line to write a second data to the second memory and applying a second potential on the first word line to write the first data to the first memory. The first potential increases by a first step voltage and the second potential increases by a second step voltage.

Abstract: According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode.

Abstract: According to an embodiment, a semiconductor memory device includes a semiconductor pillar, a first electrode film, a second electrode film, a first insulating film, a second insulating film, and a wiring film. The semiconductor member is extending in a first direction. The first electrode film is disposed at the lateral side of the semiconductor member away from the semiconductor member. The second electrode film is provided between the semiconductor member and the first electrode film. The first insulating film is provided between the semiconductor member and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode film. The wiring film is disposed in a wiring lead-out region adjacent to the memory cell region. And the first electrode film is formed of a material different from a material of the wiring film, and being electrically connected to the wiring film.

Abstract: A nonvolatile semiconductor memory device a first memory cell array layer, a first insulation layer formed on top of the first memory cell array layer, a second memory cell array layer formed on the first insulation layer, and a control gate. The first and second memory cell array layers have first and second NAND cell units provided with multiple first and second memory cells connected in series in a first direction and the first and second selection gates connected at both ends of the multiple first and second memory cells. The control gate is formed via an insulation layer between gates of the memory cells on both sides thereof in the first direction, and extends in the second direction perpendicular to the first direction.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein and a control circuit that performs a writing operation on the memory cells. The writing operation performed by the control circuit includes a pre-programming verification operation to determine a threshold level of a memory cell in an erasure state, and a program operation in which a program voltage is selected from a plurality of program voltages on the basis of a determination result of the pre-programming verification operation.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Abstract: A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

Abstract: It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract: Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.

Abstract: This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the substrate along a first direction and a second direction orthogonal to the first direction, a plurality of charge accumulation layers formed on the tunnel insulator films, respectively, a plurality of element isolation regions formed on the substrate, the element isolation regions including a plurality of trenches formed along the first direction between the tunnel insulator films, a plurality of element isolation films filled in the trenches, a plurality of inter-poly insulator films formed over the element isolation regions and on the upper and side surfaces of the charge accumulation layers along the second direction in a stripe shape, a plurality of air gaps formed between the element isolation films filled in the trenches and the inter-poly insulator films and a plurality of control gate electrodes formed on the inter-poly insulator films.