Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

Abstract: A MOS power device having: a body; gate regions on top of the body and delimiting therebetween a window; a body region, extending in the body underneath the window; a source region, extending inside the body region throughout the width of the window; body contact regions, extending through the source region up to the body region; source contact regions, extending inside the source region, at the sides of the body contact regions; a dielectric region on top of the source region; openings traversing the dielectric region on top of the body and source contact regions; and a metal region extending above the dielectric region and through the first and second openings.

Abstract: A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure c

Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

Abstract: A vertical conduction electronic power device includes respective gate, source and drain areas, realized in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be realized by a first metallization level. The gate, source and drain terminals or pads may be realized by a second metallization level. The device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area, and separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge.

Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

Abstract: A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.

Abstract: A MOS power device having: a body; gate regions on top of the body and delimiting therebetween a window; a body region, extending in the body underneath the window; a source region, extending inside the body region throughout the width of the window; body contact regions, extending through the source region up to the body region; source contact regions, extending inside the source region, at the sides of the body contact regions; a dielectric region on top of the source region; openings traversing the dielectric region on top of the body and source contact regions; and a metal region extending above the dielectric region and through the first and second openings.

Abstract: A method for forming an interface free layer of silicon on a substrate of monocrystalline silicon is provided. According to the method, a substrate of monocrystalline silicon having a surface substantially free of oxide is provided. A silicon layer in-situ doped is deposited on the surface of the substrate in an oxygen-free environment and at a temperature below 700° C. so as to produce a monocrystalline portion of the silicon layer adjacent to the substrate and a polycrystalline portion of the silicon layer spaced apart from the substrate. The silicon layer is heated so as to grow the monocrystalline portion of the silicon layer through a part of the polycrystalline portion of the silicon layer. Also provided is a method for manufacturing a bipolar transistor.

Abstract: A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.

Abstract: Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconductor layer with an opening over the body region, polysilicon regions superimposed to the gate oxide layer, and regions of a first insulating material superimposed to the polysilicon regions. The device includes regions of a second insulating material situated on a side of both the polysilicon regions and the regions of a first insulating material and over zones of the gate oxide layer situated near the opening on the body region, oxide regions interposed between the polysilicon regions and the regions of a second insulating material, oxide spacers superimposed to the regions of a second insulating material.

Abstract: A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.

Abstract: A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon includes carrying out, after having loaded the wafer inside the heated chamber of the reactor and evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally between 500 and 1200° C. and at a vacuum generally between 0.1 Pa and 60000 Pa. The treatment is performed at a time generally between 0.1 and 120 minutes, to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux. After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally between 700 and 1000° C. with nitrogen protoxide (N2O) for a time generally between 0.

Abstract: A MOS technology power device includes a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window.

Abstract: A method for forming an interface free layer of silicon on a substrate of monocrystalline silicon is provided. According to the method, a substrate of monocrystalline silicon having a surface substantially free of oxide is provided. A silicon layer in-situ doped is deposited on the surface of the substrate in an oxygen-free environment and at a temperature below 700° C. so as to produce a monocrystalline portion of the silicon layer adjacent to the substrate and a polycrystalline portion of the silicon layer spaced apart from the substrate. The silicon layer is heated so as to grow the monocrystalline portion of the silicon layer through a part of the polycrystalline portion of the silicon layer. Also provided is a method for manufacturing a bipolar transistor.

Abstract: A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.

Abstract: A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon includes carrying out, after having loaded the wafer inside the heated chamber of the reactor and evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally between 500 and 1200° C. and at a vacuum generally between 0.1 Pa and 60000 Pa. The treatment is performed at a time generally between 0.1 and 120 minutes, to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux. After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally between 700 and 1000° C. with nitrogen protoxide (N2O) for a time generally between 0.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.