Abstract: Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconductor layer with an opening over the body region, polysilicon regions superimposed to the gate oxide layer, and regions of a first insulating material superimposed to the polysilicon regions. The device includes regions of a second insulating material situated on a side of both the polysilicon regions and the regions of a first insulating material and over zones of the gate oxide layer situated near the opening on the body region, oxide regions interposed between the polysilicon regions and the regions of a second insulating material, oxide spacers superimposed to the regions of a second insulating material.

Abstract: A process for manufacturing high-density MOS-technology power devices includes the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; forming an insulating material layer over the insulated gate layer; selectively removing the insulating material layer and the underlying insulated gate layer to form a plurality of elongated windows having two elongated edges and two short edges, delimiting respective uncovered surface stripes of the semiconductor material layer; implanting a high dose of a first dopant of the first conductivity type along two directions which lie in a plane transversal to said elongated windows and orthogonal to the semiconductor material layer surface, and which are substantially symmetrically tilted at a first prescribed angle with respect to a direction orthogonal to the semiconductor material layer surface, the first angle depending on the overall thickness of the insulated gate layer and of the in

Abstract: Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconductor layer with an opening over the body region, polysilicon regions superimposed to the gate oxide layer, and regions of a first insulating material superimposed to the polysilicon regions. The device includes regions of a second insulating material situated on a side of both the polysilicon regions and the regions of a first insulating material and over zones of the gate oxide layer situated near the opening on the body region, oxide regions interposed between the polysilicon regions and the regions of a second insulating material, oxide spacers superimposed to the regions of a second insulating material.

Abstract: Semiconductor device for high voltages including at least one power component and at least one edge termination. The edge termination includes a voltage divider including a plurality of MOS transistors in series, and the edge termination is connected between non-driveble terminals of said power component.

Abstract: An amplifier stage having a first and a second transistor connected in series to each other between a first and a second reference potential line. The first transistor has a control terminal connected to an input of the amplifier stage through a first inductor, a first terminal connected to the second reference potential line through a second inductor, and a third terminal connected to a first terminal of the second transistor. The second transistor has a second terminal forming an output of the amplifier stage, and connected to the first reference potential line through a load resistor. To improve the noise figure, a matching capacitor is connected between the control terminal and the first terminal of the first transistor.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.

Abstract: An electronic semiconductor device (20) with a control electrode (19) consisting of self-aligned polycrystalline silicon (4) and silicide (12), of the type in which said control electrode (19) is formed above a portion (1) of semiconductor material which accommodates active areas (9) of the device (20) laterally with respect to the electrode, has the active areas (9) at least partially protected by an oxide layer (10) while the silicide layer (12) is obtained by means of direct reaction between a cobalt film deposited on the polycrystalline silicon (4) and on the oxide layer (10). (FIG.

Abstract: A zero thermal budget manufacturing process for a MOS-technology power device.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window.

Abstract: A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of body stripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: A high-speed MOS-technology power device integrated structure includes a plurality of elementary functional units formed in a lightly doped semiconductor layer of a first conductivity type, the elementary functional units including channel regions of a second conductivity type covered by a conductive insulated gate layer including a polysilicon layer; the conductive insulated gate layer also including a highly conductive layer superimposed over the polysilicon layer and having a resistivity much lower than the resistivity of the polysilicon layer, so that a resistance introduced by the polysilicon layer is shunted with a resistance introduced by the highly conductive layer and the overall resistivity of the insulated gate layer is lowered.

Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N- epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.