Patents by Inventor Gottfried Beer

Gottfried Beer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200303340
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Application
    Filed: April 3, 2020
    Publication date: September 24, 2020
    Inventors: Gottfried BEER, Irmgard ESCHER-POEPPEL
  • Patent number: 10651898
    Abstract: A ferrite antenna is disclosed. The ferrite antenna includes a ferrite core a first main face, a second main face opposite to the first main face, and side faces connecting the first and second main faces. A first plurality of conductor wires are disposed at the first main face of the ferrite core; a second plurality of conductor wires disposed at the second main face of the ferrite core. A first connection member is disposed at a first side face of the ferrite core, the first connection member including a first plurality of connection wires; and a second connection member is disposed at a second side face of the ferrite core, the second connection member including a second plurality of connection wires; wherein the first and second pluralities of conductor wires and the first and second plurality of connection wires are interconnected in such a way that they form an antenna coil, wherein the ferrite core is disposed in the interior space of the antenna coil.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: May 12, 2020
    Assignee: Infineon Technologies AG
    Inventors: Walther Pachler, Gottfried Beer, Juergen Hoelzl, Juergen Schilling, Harald Witschnig
  • Patent number: 10643971
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: May 5, 2020
    Assignee: Intel Deutschland GMBH
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Publication number: 20200013751
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Application
    Filed: August 15, 2019
    Publication date: January 9, 2020
    Inventors: Gottfried BEER, Irmgard ESCHER-POEPPEL
  • Patent number: 10522433
    Abstract: A package which comprises a chip carrier made of a first material, a body made of a second material differing from the first material and being arranged on the chip carrier so as to form a cavity, a semiconductor chip arranged at least partially in the cavity, and a laminate encapsulating at least one of at least part of the chip carrier, at least part of the body and at least part of the semiconductor chip.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 31, 2019
    Assignee: Infineon Technologies AG
    Inventors: Juergen Hoegerl, Horst Theuss, Gottfried Beer
  • Patent number: 10438926
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: October 8, 2019
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Publication number: 20190221521
    Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 18, 2019
    Inventors: Olaf Hohlfeld, Juergen Hoegerl, Gottfried Beer, Magdalena Hoier, Georg Meyer-Berg
  • Patent number: 10295570
    Abstract: The electronic device for sensing a current comprises a semiconductor chip comprising a main face, an electronic circuit integrated in the semiconductor chip, a redistribution metallization layer disposed above the main face of the semiconductor chip, a current path formed in the redistribution metallization layer, the current path forming a resistor that is connected at two resistance defining end points to the electronic circuit for sensing a current flowing through the current path, and external contact elements connected with the redistribution metallization layer for feeding a current to be sensed into the current path.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 21, 2019
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Wolfgang Furtner
  • Patent number: 10241088
    Abstract: A photo-acoustic gas sensor includes a light emitter unit having a light emitter configured to emit a beam of light pulses with a predetermined repetition frequency and a wavelength corresponding to an absorption band of a gas to be sensed, and a detector unit having a microphone. The light emitter unit is arranged so that the beam of light pulses traverses an area configured to accommodate the gas. The detector unit is arranged so that the microphone can receive a signal oscillating with the repetition frequency.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: March 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Horst Theuss, Gottfried Beer, Sebastian Beer, Alfons Dehe, Franz Jost, Stefan Kolb, Guenther Ruhl, Rainer Markus Schaller
  • Patent number: 10211158
    Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: February 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Juergen Hoegerl, Gottfried Beer, Magdalena Hoier, Georg Meyer-Berg
  • Patent number: 10102967
    Abstract: A method for manufacturing an inductor core is developed, wherein the method comprises the following: Forming a first electrical conductor on a first surface of a plate-shaped magnetic core; forming a second electrical conductor on a second surface of the plate-shaped magnetic core, which is opposite the first surface; and forming the inductor core by dicing the plate-shaped magnetic core transverse to the first electrical conductor and second electrical conductor.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: October 16, 2018
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Bernhard Knott, Rainer Leuschner
  • Patent number: 10090251
    Abstract: A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: October 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Peter Ossimitz, Gottfried Beer, Juergen Hoegerl, Andreas Munding
  • Patent number: 10008470
    Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: June 26, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Gottfried Beer, Walter Hartner
  • Patent number: 9984928
    Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: May 29, 2018
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Gottfried Beer, Edward Fuergut, Juergen Hoegerl, Peter Kanschat
  • Patent number: 9978720
    Abstract: An insulated chip comprising a semiconductor chip comprising at least one chip pad and an electrically insulating layer surrounding at least part of the semiconductor chip.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies AG
    Inventors: Horst Theuss, Gottfried Beer, Juergen Hoegerl
  • Patent number: 9859251
    Abstract: A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Peter Ossimitz
  • Patent number: 9818730
    Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: November 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
  • Publication number: 20170316994
    Abstract: A package which comprises a chip carrier made of a first material, a body made of a second material differing from the first material and being arranged on the chip carrier so as to form a cavity, a semiconductor chip arranged at least partially in the cavity, and a laminate encapsulating at least one of at least part of the chip carrier, at least part of the body and at least part of the semiconductor chip.
    Type: Application
    Filed: April 14, 2017
    Publication date: November 2, 2017
    Inventors: Juergen HOEGERL, Horst THEUSS, Gottfried BEER
  • Publication number: 20170288176
    Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 5, 2017
    Inventors: Gottfried Beer, Walter Hartner
  • Patent number: 9721920
    Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: August 1, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Gottfried Beer, Walter Hartner