Patents by Inventor Gottfried Beer

Gottfried Beer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160084887
    Abstract: The electronic device for sensing a current comprises a semiconductor chip comprising a main face, an electronic circuit integrated in the semiconductor chip, a redistribution metallization layer disposed above the main face of the semiconductor chip, a current path formed in the redistribution metallization layer, the current path forming a resistor that is connected at two resistance defining end points to the electronic circuit for sensing a current flowing through the current path, and external contact elements connected with the redistribution metallization layer for feeding a current to be sensed into the current path.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 24, 2016
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gottfried Beer, Wolfgang Furtner
  • Patent number: 9287206
    Abstract: A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being aligned with the through-holes. An encapsulant material is applied over the semiconductor chip.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: March 15, 2016
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Patent number: 9196510
    Abstract: A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: November 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Juergen Hoegerl, Gottfried Beer, Magdalena Hoier
  • Publication number: 20150333023
    Abstract: A semiconductor device includes a semiconductor chip and a plurality of electrical contact pads disposed on a main face of the semiconductor chip, wherein the electrical contact pads each include a layer stack, each layer stack having one and the same order of layers, and wherein the electrical contact pads are both solderable and bondable.
    Type: Application
    Filed: May 19, 2015
    Publication date: November 19, 2015
    Inventors: Gottfried Beer, Raimund Foerg, Juergen Hoegerl
  • Publication number: 20150317553
    Abstract: In various embodiments, a smart card module is provided. The smart card module includes a carrier having a first main surface and a second main surface opposite the first main surface. The carrier has at least one plated-through hole. The smart card module further includes a contact array arranged above the first main surface of the carrier and having a plurality of electrical contacts. At least one electrical contact of the plurality of electrical contacts is electrically connected to the plated-through hole. The smart card module further includes a chip arranged above the second main surface. The chip is electrically coupled to at least one electrical contact of the plurality of electrical contacts by the plated-through hole. The smart card module further includes at least one optoelectronic component arranged above the second main surface and electrically conductively connected to the chip.
    Type: Application
    Filed: April 28, 2015
    Publication date: November 5, 2015
    Inventors: Frank Pueschner, Thomas Spoettl, Jens Pohl, Gottfried Beer
  • Patent number: 9147585
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: September 29, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kilger, Ulrich Wachter, Dominic Maier, Gottfried Beer
  • Patent number: 9129959
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite from the first main face. The second main face includes at least one electrical contact element. The semiconductor chips are placed on a carrier. A material layer is applied into intermediate spaces between adjacent semiconductor chips. The carrier is removed and a first electrical contact layer is applied to the first main faces of the semiconductor chips so that the electrical contact layer is electrically connected with each one of the electrical contact elements.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: September 8, 2015
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Irmgard Escher-Poeppel, Gottfried Beer
  • Patent number: 9082644
    Abstract: A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: July 14, 2015
    Assignee: Infineon Technologies AG
    Inventors: Peter Ossimitz, Matthias von Daak, Gottfried Beer
  • Patent number: 9064869
    Abstract: The semiconductor module includes a carrier, a plurality of semiconductor transistor chips disposed on the carrier, a plurality of semiconductor diode chips disposed on the carrier, an encapsulation layer disposed above the semiconductor transistor chips and the semiconductor diode chips, and a metallization layer disposed above the encapsulation layer. The metallization layer includes a plurality of metallic areas forming electrical connections between selected ones of the semiconductor transistor chips and the semiconductor diode chips.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: June 23, 2015
    Assignee: Infineon Technologies AG
    Inventors: Juergen Hoegerl, Edward Fuergut, Gottfried Beer, Olaf Hohlfeld
  • Publication number: 20150170835
    Abstract: A method for manufacturing an inductor core is developed, wherein the method comprises the following: Forming a first electrical conductor on a first surface of a plate-shaped magnetic core; forming a second electrical conductor on a second surface of the plate-shaped magnetic core, which is opposite the first surface; and forming the inductor core by dicing the plate-shaped magnetic core transverse to the first electrical conductor and second electrical conductor.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 18, 2015
    Inventors: Gottfried Beer, Bernhard Knott, Rainer Leuschner
  • Publication number: 20150162318
    Abstract: In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.
    Type: Application
    Filed: December 10, 2013
    Publication date: June 11, 2015
    Applicant: Infineon Technologies AG
    Inventors: Robert Allinger, Gottfried Beer, Juergen Hoegerl
  • Publication number: 20150145149
    Abstract: A method of manufacturing a semiconductor device package includes encapsulating at least partially a plurality of semiconductor chips with encapsulating material to form an encapsulation body. The encapsulation body has a first main surface and a second main surface. At least one of a metal layer and an organic layer is formed over the first main surface of the encapsulation body. At least one trace of the at least one of the metal layer and the organic layer is removed by laser ablation. The encapsulation body is then separated into a plurality of semiconductor device packages along the at least one trace.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Inventors: Ulrich Wachter, Eva Wagner, Gottfried Beer
  • Patent number: 9041505
    Abstract: In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Urs Elrod, Christiane Brunner, Thomas Kilger
  • Publication number: 20150130048
    Abstract: A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Inventors: Olaf Hohlfeld, Juergen Hoegerl, Gottfried Beer, Magdalena Hoier
  • Patent number: 8990744
    Abstract: The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: March 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Dominic Maier, Gerhard Metzger-Br├╝ckl, Rainer Leuschner
  • Publication number: 20150076636
    Abstract: A current sensor device for sensing a measuring current includes a semiconductor chip having a magnetic field sensitive element. The current sensor device further includes an encapsulant embedding the semiconductor chip. A conductor configured to carry the measuring current is electrically insulated from the magnetic field sensitive element. A redistribution structure includes a first metal layer having a first structured portion which forms part of the conductor.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Inventors: Gottfried Beer, Volker Strutz, Horst Theuss
  • Publication number: 20150061100
    Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 5, 2015
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
  • Publication number: 20150061144
    Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.
    Type: Application
    Filed: September 3, 2014
    Publication date: March 5, 2015
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
  • Publication number: 20150064846
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
    Type: Application
    Filed: November 7, 2014
    Publication date: March 5, 2015
    Inventors: Thomas Kilger, Ulrich Wachter, Dominic Maier, Gottfried Beer
  • Publication number: 20150054159
    Abstract: The semiconductor module includes a carrier, a plurality of semiconductor transistor chips disposed on the carrier, a plurality of semiconductor diode chips disposed on the carrier, an encapsulation layer disposed above the semiconductor transistor chips and the semiconductor diode chips, and a metallization layer disposed above the encapsulation layer. The metallization layer includes a plurality of metallic areas forming electrical connections between selected ones of the semiconductor transistor chips and the semiconductor diode chips.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Inventors: Juergen Hoegerl, Edward Fuergut, Gottfried Beer, Olaf Hohlfeld