Patents by Inventor Gottfried Beer

Gottfried Beer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor Packages with Integrated Antenna and Method of Forming Thereof
    Publication number: 20140110840
    Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.
    Type: Application
    Filed: January 8, 2013
    Publication date: April 24, 2014
    Applicant: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Walter Hartner, Ottmar Geitner, Gottfried Beer, Klaus Pressel, Mehran Pour Mousavi
  • System and Method for a Coreless Transformer
    Publication number: 20140070913
    Abstract: In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 13, 2014
    Applicant: Infineon Technologies AG
    Inventors: Gottfried Beer, Urs Elrod, Christiane Brunner, Thomas Kilger
  • Method for Manufacturing an Electronic Module and an Electronic Module
    Publication number: 20140054780
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite from the first main face. The second main face includes at least one electrical contact element. The semiconductor chips are placed on a carrier. A material layer is applied into intermediate spaces between adjacent semiconductor chips. The carrier is removed and a first electrical contact layer is applied to the first main faces of the semiconductor chips so that the electrical contact layer is electrically connected with each one of the electrical contact elements.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Edward Fuergut, Irmgard Escher-Poeppel, Gottfried Beer
  • Method for fabricating a semiconductor and semiconductor package
    Patent number: 8658468
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: February 25, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Electronic Device and Method of Fabricating an Electronic Device
    Publication number: 20140042603
    Abstract: A semiconductor device includes an electrically conducting carrier and a semiconductor chip disposed over the carrier. The semiconductor device also includes a porous diffusion solder layer provided between the carrier and the semiconductor chip.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Khalil Hosseini, Joachim Mahler, Ivan Nikitin, Gottfried Beer
  • Method and system for routing electrical connections of semiconductor chips
    Patent number: 8598709
    Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: December 3, 2013
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gottfried Beer, Christian Geissler, Thomas Ort, Klaus Pressel, Bernd Waidhas, Andreas Wolter
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME
    Publication number: 20130309864
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Application
    Filed: November 8, 2012
    Publication date: November 21, 2013
    Inventors: Hans-Joachim BARTH, Mathias VAUPEL, Rainer STEINER, Werner ROBL, Jens POHL, Joern PLAGMANN, Gottfried BEER
  • METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE
    Publication number: 20130267063
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Application
    Filed: June 4, 2013
    Publication date: October 10, 2013
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • System and method for a coreless transformer
    Patent number: 8552828
    Abstract: In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: October 8, 2013
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Urs Elrod, Christiane Brunner, Thomas Kilger
  • Method for fabricating a semiconductor and semiconductor package
    Patent number: 8492200
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: July 23, 2013
    Assignee: Intel Mobile Communications GmbH
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Heat treatment for a panel and apparatus for carrying out the heat treatment method
    Patent number: 8431063
    Abstract: A heat treatment method is provided for a panel. The panel includes a plastic housing composition, in which semiconductor chips are embedded by their rear sides and edge sides, and the top sides of the semiconductor chips form a coplanar area with the plastic housing composition. The panel is fixed by its underside on a holder, and a temperature gradient (?T) is then generated between top side and the underside of the panel. The temperature gradient (?T) is then maintained for at least one delimited or selected time period. The panel is then cooled to room temperature (TR).
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: April 30, 2013
    Assignee: Intel Mobile Communications GmbH
    Inventors: Gottfried Beer, Markus Brunnbauer, Edward Fuergut
  • Method and system for routing electrical connections of semiconductor chips
    Patent number: 8415803
    Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: April 9, 2013
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gottfried Beer, Christian Geissler, Thomas Ort, Klaus Pressel, Bernd Waidhas, Andreas Wolter
  • Semiconductor device and manufacturing method
    Patent number: 8338936
    Abstract: A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: December 25, 2012
    Assignee: Infineon Technologies AG
    Inventors: Klaus Pressel, Gottfried Beer
  • METHOD FOR FABRICATING A SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE
    Publication number: 20120319298
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Application
    Filed: August 9, 2012
    Publication date: December 20, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
    Publication number: 20120319304
    Abstract: A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer.
    Type: Application
    Filed: August 27, 2012
    Publication date: December 20, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Klaus Pressel, Gottfried Beer
  • Device fabricated using an electroplating process
    Patent number: 8334202
    Abstract: A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: December 18, 2012
    Assignee: Infineon Technologies AG
    Inventors: Jens Pohl, Hans-Joachim Barth, Gottfried Beer, Rainer Steiner, Werner Robl, Mathias Vaupel
  • Semiconductor structure and method for making same
    Patent number: 8330274
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Gottfried Beer, Joern Plagmann, Jens Pohl, Werner Robl, Rainer Steiner, Mathias Vaupel
  • Method of manufacturing a semiconductor structure
    Patent number: 8318540
    Abstract: A method of manufacturing a semiconductor structure. One embodiment produces a substrate having at least two semiconductor chips embedded in a molded body. A layer is applied over at least one main surface of the substrate by using a jet printing process.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: November 27, 2012
    Assignee: Infineon Technologies AG
    Inventor: Gottfried Beer
  • EMBEDDED CHIP PACKAGE
    Publication number: 20120287583
    Abstract: An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip.
    Type: Application
    Filed: July 25, 2012
    Publication date: November 15, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Klaus Pressel, Gottfried Beer
  • On-Chip RF Shields with Backside Redistribution Lines
    Publication number: 20120258594
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 11, 2012
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Heinrich Koerner