Patents by Inventor Gottfried Beer

Gottfried Beer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170288176
    Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 5, 2017
    Inventors: Gottfried Beer, Walter Hartner
  • Patent number: 9721920
    Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: August 1, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Gottfried Beer, Walter Hartner
  • Patent number: 9711462
    Abstract: In various embodiments, a package arrangement may be provided. The package arrangement may include at least one chip. The package arrangement may further include encapsulation material at least partially encapsulating the chip. The package arrangement may also include a redistribution structure over a first side of the chip. The package arrangement may further include a metal structure over a second side of the chip. The second side may be opposite the first side. The package arrangement may additionally include at least one of a semiconductor structure and an electrically conductive plastic material structure electrically coupled to the redistribution structure and the metal structure to form a current path between the redistribution structure and the metal structure.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: July 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Dominic Maier, Ulrich Wachter, Daniel Kehrer
  • Patent number: 9620459
    Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
  • Patent number: 9620457
    Abstract: A method of manufacturing a semiconductor device package includes encapsulating at least partially a plurality of semiconductor chips with encapsulating material to form an encapsulation body. The encapsulation body has a first main surface and a second main surface. At least one of a metal layer and an organic layer is formed over the first main surface of the encapsulation body. At least one trace of the at least one of the metal layer and the organic layer is removed by laser ablation. The encapsulation body is then separated into a plurality of semiconductor device packages along the at least one trace.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Eva Wagner, Gottfried Beer
  • Publication number: 20170098580
    Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.
    Type: Application
    Filed: December 14, 2016
    Publication date: April 6, 2017
    Inventors: Olaf Hohlfeld, Gottfried Beer, Edward Fuergut, Juergen Hoegerl, Peter Kanschat
  • Patent number: 9589859
    Abstract: A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: March 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Edward Fuergut, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
  • Patent number: 9559065
    Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: January 31, 2017
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
  • Publication number: 20170025357
    Abstract: A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.
    Type: Application
    Filed: July 24, 2015
    Publication date: January 26, 2017
    Inventors: Peter Ossimitz, Gottfried Beer, Juergen Hoegerl, Andreas Munding
  • Patent number: 9553208
    Abstract: A current sensor device for sensing a measuring current includes a semiconductor chip having a magnetic field sensitive element. The current sensor device further includes an encapsulant embedding the semiconductor chip. A conductor configured to carry the measuring current is electrically insulated from the magnetic field sensitive element. A redistribution structure includes a first metal layer having a first structured portion which forms part of the conductor.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: January 24, 2017
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Volker Strutz, Horst Theuss
  • Publication number: 20170012355
    Abstract: A ferrite antenna is disclosed. The ferrite antenna includes a ferrite core a first main face, a second main face opposite to the first main face, and side faces connecting the first and second main faces. A first plurality of conductor wires are disposed at the first main face of the ferrite core; a second plurality of conductor wires disposed at the second main face of the ferrite core. A first connection member is disposed at a first side face of the ferrite core, the first connection member including a first plurality of connection wires; and a second connection member is disposed at a second side face of the ferrite core, the second connection member including a second plurality of connection wires; wherein the first and second pluralities of conductor wires and the first and second plurality of connection wires are interconnected in such a way that they form an antenna coil, wherein the ferrite core is disposed in the interior space of the antenna coil.
    Type: Application
    Filed: June 16, 2016
    Publication date: January 12, 2017
    Applicant: Infineon Technologies AG
    Inventors: Walther Pachler, Gottfried Beer, Juergen Hoelzl, Juergen Schilling, Harald Witschnig
  • Publication number: 20170011982
    Abstract: An insulated chip comprising a semiconductor chip comprising at least one chip pad and an electrically insulating layer surrounding at least part of the semiconductor chip.
    Type: Application
    Filed: July 5, 2016
    Publication date: January 12, 2017
    Inventors: Horst THEUSS, Gottfried BEER, Juergen HOEGERL
  • Patent number: 9496237
    Abstract: A semiconductor device includes a semiconductor chip and a plurality of electrical contact pads disposed on a main face of the semiconductor chip, wherein the electrical contact pads each include a layer stack, each layer stack having one and the same order of layers, and wherein the electrical contact pads are both solderable and bondable.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: November 15, 2016
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Raimund Foerg, Juergen Hoegerl
  • Publication number: 20160313288
    Abstract: A photo-acoustic gas sensor includes a light emitter unit having a light emitter configured to emit a beam of light pulses with a predetermined repetition frequency and a wavelength corresponding to an absorption band of a gas to be sensed, and a detector unit having a microphone. The light emitter unit is arranged so that the beam of light pulses traverses an area configured to accommodate the gas. The detector unit is arranged so that the microphone can receive a signal oscillating with the repetition frequency.
    Type: Application
    Filed: April 22, 2016
    Publication date: October 27, 2016
    Inventors: Horst Theuss, Gottfried Beer, Sebastian Beer, Alfons Dehe, Franz Jost, Stefan Kolb, Guenther Ruhl, Rainer Markus Schaller
  • Publication number: 20160225745
    Abstract: A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.
    Type: Application
    Filed: February 1, 2016
    Publication date: August 4, 2016
    Inventors: Gottfried Beer, Peter Ossimitz
  • Patent number: 9390973
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: July 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Heinrich Koerner
  • Patent number: 9384437
    Abstract: In various embodiments, a smart card module is provided. The smart card module includes a carrier having a first main surface and a second main surface opposite the first main surface. The carrier has at least one plated-through hole. The smart card module further includes a contact array arranged above the first main surface of the carrier and having a plurality of electrical contacts. At least one electrical contact of the plurality of electrical contacts is electrically connected to the plated-through hole. The smart card module further includes a chip arranged above the second main surface. The chip is electrically coupled to at least one electrical contact of the plurality of electrical contacts by the plated-through hole. The smart card module further includes at least one optoelectronic component arranged above the second main surface and electrically conductively connected to the chip.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: July 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Frank Pueschner, Thomas Spoettl, Jens Pohl, Gottfried Beer
  • Patent number: 9337155
    Abstract: A semiconductor component includes a semiconductor body having a top side and a bottom side opposite the top side. A top metallization is applied to the top side and a bottom metallization is applied to the bottom side. A moisture barrier completely seals the semiconductor body in cooperation with the top metallization and the bottom metallization.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: May 10, 2016
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Juergen Hoegerl, Thilo Stolze
  • Publication number: 20160126192
    Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 5, 2016
    Inventors: Olaf Hohlfeld, Juergen Hoegerl, Gottfried Beer, Magdalena Hoier, Georg Meyer-Berg
  • Patent number: 9331059
    Abstract: In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: May 3, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Robert Allinger, Gottfried Beer, Juergen Hoegerl