Patents by Inventor Gottfried Beer

Gottfried Beer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR FABRICATING A SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE
    Publication number: 20120258571
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Application
    Filed: June 21, 2012
    Publication date: October 11, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Method for fabricating a semiconductor and semiconductor package
    Patent number: 8258624
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: September 4, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Embedded chip package
    Patent number: 8237259
    Abstract: An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip. The electronic assembly further includes a substrate embedding the package structure.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: August 7, 2012
    Assignee: Infineon Technologies AG
    Inventors: Klaus Pressel, Gottfried Beer
  • Method for fabricating a semiconductor and semiconductor package
    Patent number: 8216881
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: July 10, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Microelectromechanical semiconductor component with cavity structure and method for producing the same
    Patent number: 8212344
    Abstract: One aspect of the invention relates to a semiconductor component with cavity structure and a method for producing the same. The semiconductor component has an active semiconductor chip with the microelectromechanical structure and a wiring structure on its top side. The microelectromechanical structure is surrounded by walls of at least one cavity. A covering, which covers the cavity, is arranged on the walls. The walls have a photolithographically patterned polymer. The covering has a layer with a polymer of identical type. In one case, the molecular chains of the polymer of the walls are crosslinked with the molecular chains of the polymer layer of the covering layer to form a dimensionally stable cavity housing.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: July 3, 2012
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Horst Theuss
  • On-chip RF shields with through substrate conductors
    Patent number: 8169059
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, the system on a chip includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary. The system on chip further includes through substrate conductors disposed in the substrate, the through substrate conductors coupled to a ground potential node, the through substrate conductors disposed around the RF component forming a fence around the RF circuit.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 1, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Oliver Nagy
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME
    Publication number: 20120080791
    Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Inventors: Hans-Joachim BARTH, Gottfried BEER, Joern PLAGMANN, Jens POHL, Werner ROBL, Rainer STEINER, Mathias VAUPEL
  • Semiconductor structure and method for making same
    Patent number: 8148257
    Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 3, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Gottfried Beer, Joern Plagmann, Jens Pohl, Werner Robl, Rainer Steiner, Mathias Vaupel
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME
    Publication number: 20120074574
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Inventors: Hans-Joachim BARTH, Gottfried BEER, Joern PLAGMANN, Jens POHL, Werner ROBL, Rainer STEINER, Mathias VAUPEL
  • METHOD AND SYSTEM FOR ROUTING ELECTRICAL CONNECTIONS OF SEMICONDUCTOR CHIPS
    Publication number: 20120049375
    Abstract: A method and a system for routing electrical connections of a plurality of chips are disclosed. In one embodiment, a semiconductor device is provided comprising at least one semiconductor chip, at least one routing plane comprising at least one routing line, and at least one connecting line electrically coupled to the at least one routing line and at least one semiconductor chip.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 1, 2012
    Inventors: Thorsten MEYER, Gottfried BEER, Christian GEISSLER, Thomas ORT, Klaus PRESSEL, Bernd WAIDHAS, Andreas WOLTER
  • Method of fabricating a semiconductor device
    Patent number: 8119452
    Abstract: One method includes fabricating a semiconductor device including providing a dielectric layer. At least one semiconductor chip is provided defining a first surface including contact elements and a second surface opposite to the first surface. The semiconductor chip is placed onto the dielectric layer with the first surface facing the dielectric layer. An encapsulant material is applied over the second surface of the semiconductor chip in a reel-to-reel process.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: February 21, 2012
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Stacked semiconductor chips
    Patent number: 8076784
    Abstract: Stacked semiconductor chips are disclosed. One embodiment provides a method including a first substrate having a first surface and an opposing second surface. The first substrate includes an array of first connection elements on the first surface of the first substrate. A second substrate has a first surface and an opposing second surface. The second substrate includes an array of second connection elements on the first surface of the second substrate. The first connection elements is attached to the second connection elements; and is thinning at least one of the first substrate and the second substrate after the attachment of the first connection elements to the second connection elements.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: December 13, 2011
    Assignee: Infineon Technologies AG
    Inventors: Markus Brunnbauer, Recai Sezi, Thorsten Meyer, Gottfried Beer
  • Semiconductor device including conductive element
    Patent number: 8072071
    Abstract: A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: December 6, 2011
    Assignee: Infineon Technologies AG
    Inventors: Rainer Steiner, Jens Pohl, Werner Robl, Markus Brunnbauer, Gottfried Beer
  • Method for Fabricating a Semiconductor Chip Package and Semiconductor Chip Package
    Publication number: 20110291256
    Abstract: A semiconductor chip includes a contact pad on a main surface of the chip. An electrically conductive layer is applied onto the contact pad. The main surface of the semiconductor chip is covered with an insulating layer. An electrically conductive contact area is formed within the insulating layer such that the contact area and the insulating layer include coplanar exposed surfaces and the contact area is electrically connected with the electrically conductive layer and includes an extension which is greater than the extension of the electrically conductive layer along a direction parallel to the main surface of the semiconductor chip.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Inventors: Rainer Steiner, Jens Pohl, Werner Robl, Gottfried Beer
  • METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    Publication number: 20110281405
    Abstract: A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being aligned with the through-holes. An encapsulant material is applied over the semiconductor chip.
    Type: Application
    Filed: July 25, 2011
    Publication date: November 17, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • SEMICONDUCTOR DEVICE WITH HOLLOW STRUCTURE
    Publication number: 20110210450
    Abstract: A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed.
    Type: Application
    Filed: May 6, 2011
    Publication date: September 1, 2011
    Inventors: Horst Theuss, Gottfried Beer
  • Semiconductor device with hollow structure
    Patent number: 7952185
    Abstract: A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: May 31, 2011
    Assignee: Infineon Technologies AG
    Inventors: Horst Theuss, Gottfried Beer
  • DEVICE FABRICATED USING AN ELECTROPLATING PROCESS
    Publication number: 20110101532
    Abstract: A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 5, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Jens Pohl, Hans-Joachim Barth, Gottfried Beer, Rainer Steiner, Werner Robl, Mathias Vaupel
  • On-chip RF shields with backside redistribution lines
    Patent number: 7936052
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 3, 2011
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Heinrich Koerner
  • Semiconductor chips for TAG applications, devices for mounting the same, and mounting method
    Patent number: 7922093
    Abstract: A TAG chip includes a magnetic coating or an electrostatically chargeable structure. A device for packing semiconductor chips includes an electromagnetic or electrostatic lifter, which picks up singulated semiconductor chips of a semiconductor wafer with a magnetic coating or including an electrostatically chargeable structure from a wafer position and deposits them in a collecting position. A mounting device includes a conveying roller with conveying receptacles for semiconductor chips, which pick up the semiconductor chips in a pick-up position with electromagnetically or electrostatically activatable conveying receptacles and, in a discharge position will discharge, via deactivation of the conveying receptacles, the semiconductor chips onto a corresponding liner or an object.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: April 12, 2011
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Werner Weber