Patents by Inventor Gregory L. Whiting

Gregory L. Whiting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230187373
    Abstract: A method of forming a charge pattern on a microchip includes depositing a first material on an insulator surface of the microchip, depositing a material having capability of forming a self-assembled monolayer on the other material, wherein the material comprises at least one material selected from the group consisting of: octadecyltrichlorosilane, phenethyltrichlorosilane, hexamethyldisilazane, allyltrimethoxysilane, or perfluorooctyltrichlorosilanem, and patterning the self-assembled monolayer to reveal a portion of the first material.
    Type: Application
    Filed: February 3, 2023
    Publication date: June 15, 2023
    Inventors: Eugene M. Chow, JenPing Lu, Armin R. Volkel, Bing R. Hsieh, Gregory L. Whiting, Sean E. Doris
  • Patent number: 11574876
    Abstract: A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and immersing the microchip in a fluid to develop charge in or on the material through interaction with the surrounding fluid.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: February 7, 2023
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Eugene M. Chow, JenPing Lu, Armin R. Volkel, Bing R. Hsieh, Gregory L. Whiting, Sean E. Doris
  • Patent number: 11417849
    Abstract: Integrated circuit structures, arrangements, and manufacturing processes are discussed herein. In one example, a method of forming a transistor structure includes forming a dielectric layer onto a gate element and forming a corrugated surface into the dielectric layer using at least an atomic layer etching (ALE) process to remove portions of the dielectric layer. The method also includes forming a semiconductor layer onto the corrugated surface and forming a source element and a drain element onto the semiconductor layer.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 16, 2022
    Assignee: The Regents of the University of Colorado, a body corporate
    Inventors: Rayshan Visvanathan, Diana Torres Sanchez, Gregory L. Whiting
  • Patent number: 11122683
    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 14, 2021
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Tse Nga Ng, Ping Mei, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
  • Publication number: 20200381641
    Abstract: Integrated circuit structures, arrangements, and manufacturing processes are discussed herein. In one example, a method of forming a transistor structure includes forming a dielectric layer onto a gate element and forming a corrugated surface into the dielectric layer using at least an atomic layer etching (ALE) process to remove portions of the dielectric layer. The method also includes forming a semiconductor layer onto the corrugated surface and forming a source element and a drain element onto the semiconductor layer.
    Type: Application
    Filed: June 1, 2020
    Publication date: December 3, 2020
    Inventors: Rayshan Visvanathan, Diana Torres Sanchez, Gregory L. Whiting
  • Patent number: 10818842
    Abstract: A method and system utilizes ink jetting or printing of surface work function modification material or solution to form modified p-type and/or n-type electrodes. The proposed method is suitable for making complementary OTFT circuits in roll-to-roll fabrication environment.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 27, 2020
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Robert A. Street, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
  • Patent number: 10648491
    Abstract: A stress-engineered frangible structure includes multiple discrete glass members interconnected by inter-structure bonds to form a complex structural shape. Each glass member includes strengthened (i.e., by way of stress-engineering) glass material portions that are configured to transmit propagating fracture forces throughout the glass member. Each inter-structure bond includes a bonding member (e.g., glass-frit or adhesive) connected to weaker (e.g., untreated, unstrengthened, etched, or thinner) glass member region(s) disposed on one or both interconnected glass members that function to reliably transfer propagating fracture forces from one glass member to other glass member. An optional trigger mechanism generates an initial fracture force in a first (most-upstream) glass member, and the resulting propagating fracture forces are transferred by way of inter-structure bonds to all downstream glass members.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: May 12, 2020
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Scott J. H. Limb, Gregory L. Whiting
  • Publication number: 20200052214
    Abstract: A method and system utilizes ink jetting or printing of surface work function modification material or solution to form modified p-type and/or n-type electrodes. The proposed method is suitable for making complementary OTFT circuits in roll-to-roll fabrication environment.
    Type: Application
    Filed: October 22, 2019
    Publication date: February 13, 2020
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Ping Mei, Robert A. Street, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
  • Publication number: 20200027847
    Abstract: A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger device operably mounted on a surface thereof. An integrated circuit (IC) die is then bonded to the interposer, and the interposer is mounted to a package structure where it serves, under normal operating conditions, to operably connect the IC die to the package I/O pins/balls. During a transient event (e.g., when unauthorized tampering is detected), a trigger signal is transmitted to the trigger device, causing the trigger device to generate an initial fracture force that is applied onto the glass-based interposer substrate. The interposer is configured such that the initial fracture force propagates through the glass-based interposer substrate with sufficient energy to both entirely powderize the interposer, and to transfer to the IC die, whereby the IC die also powderizes (i.e., visually disappears).
    Type: Application
    Filed: April 16, 2019
    Publication date: January 23, 2020
    Inventors: Scott J.H. Limb, Gregory L. Whiting
  • Patent number: 10541215
    Abstract: A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger device operably mounted on a surface thereof. An integrated circuit (IC) die is then bonded to the interposer, and the interposer is mounted to a package structure where it serves, under normal operating conditions, to operably connect the IC die to the package I/O pins/balls. During a transient event (e.g., when unauthorized tampering is detected), a trigger signal is transmitted to the trigger device, causing the trigger device to generate an initial fracture force that is applied onto the glass-based interposer substrate. The interposer is configured such that the initial fracture force propagates through the glass-based interposer substrate with sufficient energy to both entirely powderize the interposer, and to transfer to the IC die, whereby the IC die also powderizes (i.e., visually disappears).
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: January 21, 2020
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Scott J. H. Limb, Gregory L. Whiting
  • Patent number: 10490746
    Abstract: A method and system utilizes ink jetting or printing of surface work function modification material or solution to form modified p-type and/or n-type electrodes. The proposed method is suitable for making complementary OTFT circuits in roll-to-roll fabrication environment.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: November 26, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Robert A. Street, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
  • Patent number: 10466193
    Abstract: A printed resistive gas detector configuration that is simple, inexpensive and compact, fabricated for incorporation into an electronic device, such as an electronic computing and/or communication device, the printed resistive gas detector configuration designed to continuously monitor for predetermined types of gasses. The printed resistive gas detector configuration manufactured by the use of printing technology to print on a flexible substrate.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: November 5, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Robert A. Street, David Eric Schwartz, Ping Mei, Brent S. Krusor, Jonathan Rivnay, Yong Zhang, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
  • Publication number: 20190186513
    Abstract: A stress-engineered frangible structure includes multiple discrete glass members interconnected by inter-structure bonds to form a complex structural shape. Each glass member includes strengthened (i.e., by way of stress-engineering) glass material portions that are configured to transmit propagating fracture forces throughout the glass member. Each inter-structure bond includes a bonding member (e.g., glass-frit or adhesive) connected to weaker (e.g., untreated, unstrengthened, etched, or thinner) glass member region(s) disposed on one or both interconnected glass members that function to reliably transfer propagating fracture forces from one glass member to other glass member. An optional trigger mechanism generates an initial fracture force in a first (most-upstream) glass member, and the resulting propagating fracture forces are transferred by way of inter-structure bonds to all downstream glass members.
    Type: Application
    Filed: February 12, 2019
    Publication date: June 20, 2019
    Inventors: Scott J. H. Limb, Gregory L. Whiting
  • Publication number: 20190124757
    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.
    Type: Application
    Filed: November 14, 2018
    Publication date: April 25, 2019
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Tse Nga Ng, Ping Mei, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
  • Patent number: 10262954
    Abstract: A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger device operably mounted on a surface thereof. An integrated circuit (IC) die is then bonded to the interposer, and the interposer is mounted to a package structure where it serves, under normal operating conditions, to operably connect the IC die to the package I/O pins/balls. During a transient event (e.g., when unauthorized tampering is detected), a trigger signal is transmitted to the trigger device, causing the trigger device to generate an initial fracture force that is applied onto the glass-based interposer substrate. The interposer is configured such that the initial fracture force propagates through the glass-based interposer substrate with sufficient energy to both entirely powderize the interposer, and to transfer to the IC die, whereby the IC die also powderizes (i.e., visually disappears).
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 16, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Scott J. H. Limb, Gregory L. Whiting
  • Patent number: 10202990
    Abstract: A stress-engineered frangible structure includes multiple discrete glass members interconnected by inter-structure bonds to form a complex structural shape. Each glass member includes strengthened (i.e., by way of stress-engineering) glass material portions that are configured to transmit propagating fracture forces throughout the glass member. Each inter-structure bond includes a bonding member (e.g., glass-frit or adhesive) connected to weaker (e.g., untreated, unstrengthened, etched, or thinner) glass member region(s) disposed on one or both interconnected glass members that function to reliably transfer propagating fracture forces from one glass member to other glass member. An optional trigger mechanism generates an initial fracture force in a first (most-upstream) glass member, and the resulting propagating fracture forces are transferred by way of inter-structure bonds to all downstream glass members.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: February 12, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Scott J. H. Limb, Gregory L. Whiting
  • Patent number: 10206288
    Abstract: A hybrid electronic assembly includes a substrate having conductive circuit tracings, and includes at least one opening defined within length and width dimensions of the substrate. An electronic circuit component which has conductive circuit tracings, and is located within the at least one opening of the substrate. An alignment area where a first surface of the substrate and a first surface of the electronic circuit component are aligned in a substantially planar flat relationship with the electronic circuit component. A non-alignment area where a second surface of the substrate and a second surface of the electronic circuit component are in a non-aligned relationship.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: February 12, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Gregory L. Whiting, Brent S. Krusor
  • Patent number: 10165677
    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: December 25, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Tse Nga Ng, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
  • Patent number: RE47570
    Abstract: A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: August 13, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Scott J. H. Limb, Gregory L. Whiting, Sean R. Garner, JengPing Lu, Dirk De Bruyker
  • Patent number: RE49059
    Abstract: A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 3, 2022
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Scott J. H. Limb, Gregory L. Whiting, Sean R. Garner, JengPing Lu, Dirk De Bruyker