Abstract: A shift register unit includes an input sub-circuit, a pull-down node driving sub-circuit and an output sub-circuit. The pull-down node driving sub-circuit includes a first connection unit, a first voltage-reduction unit and a second connection unit, and configured to: under the control of the first voltage signal terminal and the pull-up node, transmit a first voltage signal from the first voltage signal terminal to the first pull-down node via the first connection unit, and reduce a voltage applied to the second connection unit via the first voltage-reduction unit; and transmit a second voltage signal from the second voltage signal terminal to the first pull-down node via the second connection unit under the control of the pull-up node.

Abstract: A method of manufacturing an array substrate includes: forming a first semiconductor pattern and a first insulating layer group sequentially on a base substrate; forming a second semiconductor pattern and a second insulating layer group sequentially on the first insulating layer group; forming two first via holes in the first insulating layer group and the second insulating layer group to expose the first semiconductor pattern, annealing the exposed first semiconductor pattern and then removing an oxide layer on a surface of the first semiconductor pattern; forming connecting wires in the first via holes; forming second via holes in the second insulating layer group to expose the second semiconductor pattern, and forming a first source electrode and a first drain electrode in the second via holes such that the first source electrode or the first drain electrode covers and is connected to one of the connecting wires.

Abstract: A display substrate and a manufacturing method thereof and a display device are disclosed. The manufacturing method of the display substrate includes: forming a first display electrode; and forming a thin film transistor, which includes forming a semiconductor layer; The first display electrode and the semiconductor layer are in one same layer, and a step of forming the first display electrode is performed before performing a step of forming the semiconductor layer.

Abstract: The present application relates to a substrate transfer device, comprising a horizontally arranged cross beam, and support beams longitudinally arranged at two ends of the cross beam, wherein a substrate carrier is suspended on the cross beam, the substrate carrier is located between the two support beams, and the substrate carrier is parallel to a plane where the two support beams are located, the substrate carrier comprises two side walls oppositely arranged in a horizontal direction, and each of the support beams is provided with an auxiliary clamping structure for clamping the substrate carrier during transferring of the substrate carrier.

Abstract: The present disclosure provides an electrochemical deposition apparatus set. The electrochemical deposition apparatus set includes: an electrochemical deposition device configured to form an electrochemical deposition film layer on an area to be coated of a substrate; an antioxidation treatment device located on a side of the electrochemical deposition device and configured to performing antioxidation treatment on the substrate formed with the electrochemical deposition film layer; a transmission device configured to carry the substrate and drive the substrate to move at least from the electrochemical deposition device to the antioxidation treatment device.

Abstract: The present disclosure provides a carrier liquid leakage preventing device and an electrochemical deposition apparatus. The carrier liquid leakage preventing device is used for containing liquid medicine dripping from a carrier; the carrier liquid leakage preventing device comprises: a guide rail disposed along a first direction, the first direction is a vertical direction perpendicular to the horizontal plane or a direction at an angle to the horizontal plane; a leakage preventing groove provided on the guide rail and capable of performing a lifting movement along the guide rail so as to move above or below the carrier; and a driver for driving the lifting movement of the leakage preventing groove.

Abstract: Disclosed are a micro-lens structure, a displaying device, and a machining method of the micro-lens structure. The micro-lens structure specifically comprises: micro-lens units distributed in an array, wherein each micro-lens unit comprises at least two micro-lenses made of a photoresist, and the at least two micro-lenses have different arch heights.

Abstract: The present disclosure provides a lens assembly and a fabricating method thereof, and a displaying device, and relates to the technical field of optics. The lens assembly includes a plurality of lenses that are not connected to each other and a plurality of isolating parts, the isolating parts are provided between neighboring instances of the lenses, and a refractive index of the isolating parts is different from a refractive index of the lenses.

Abstract: Embodiments of the present application disclose a method for manufacturing a naked-eye 3D device and a naked-eye 3D device. The method includes: forming a display module including a plurality of pixel islands; forming a spacer layer on the display module; and forming a micro-lens array on the spacer layer, wherein the spacer layer is formed to have a thickness such that the plurality of pixel islands are located at a focal plane of the micro-lens array. The method further includes: forming an alignment mark between the spacer layer and the display module, wherein the alignment mark is used for, when forming the micro-lens array, aligning each micro-lens in the micro-lens array with one of the plurality of pixel islands.

Abstract: An array substrate is provided. The array substrate includes a base substrate; a first bonding pad layer including a plurality of first bonding pads on a first side of the base substrate; a second bonding pad layer including a plurality of second bonding pads on a second side of the base substrate, wherein the second side is opposite to the first side; and a plurality of signal lines on a side of the second bonding pad layer away from the base substrate. A respective one of the plurality of second bonding pads extends through the base substrate to electrically connect to a respective one of the plurality of first bonding pads. The respective one of the plurality of first bonding pads includes a protruding portion protruding away from the first side of the base substrate along a direction from the second side to the first side.

Abstract: The present disclosure relates to a display device and a preparation method of the display device, and relates to the field of display technology. The display device includes a lower polarizing plate and an upper polarizing plate arranged oppositely, and an embedded polarizing layer located between the lower polarizing plate and the upper polarizing plate. The embedded polarizing layer is located between the lower polarizing plate and the upper polarizing plate, and includes a first orientation layer, a second orientation layer, and a polarizing material layer. The polarizing material layer includes a liquid crystal material. The material layer is arranged between the first orientation layer and the second orientation layer, and is in contact with both the first orientation layer and the second orientation layer. The present disclosure can enhance the contrast of the display device and improve the display effect of the display device.

Abstract: A digital exposure apparatus includes a lens array, the lens array at least including a first lens unit and a second lens unit, a light transposition assembly arranged on an exit light path of the second lens unit, and the light transposition assembly being used for controlling a light exiting from the second lens unit to be transposed with respect to an exposure direction of the digital exposure apparatus. When the digital exposure apparatus is used for exposure, a light passing through the first lens unit and a light penetrating through the second lens unit are needed to expose the same position for multiple times.

Abstract: A gate driving unit includes: a pull-up node denoising circuit; a pull-down node control circuit; a pull-up node control circuit; and an energy storage circuit. The pull-up node denoising circuit is configured to, under control of a potential of the pull-down node, control coupling or discoupling between the first pull-up node and the input terminal. The pull-down node control circuit is configured to, under control of a control voltage, control the potential of the pull-down node; under control of a potential of the second pull-up node, control coupling or discoupling between the pull-down node and the input terminal. The pull-up node control circuit is configured to, under control of an anti-leakage control voltage, control coupling or discoupling between the first pull-up node and the second pull-up node, and configured to maintain the potential of the second pull-up node. The energy storage circuit is configured to store electric energy.

Abstract: A driving backplane, a display panel and a display apparatus are provided. The driving backplane includes: a base substrate, and a plurality of connection electrode groups and a plurality of correction structures disposed on the base substrate, each of the connection electrode groups includes: a first connection electrode and a second connection electrode the first connection electrode and the second connection electrode are arranged on a same layer; a first gap is formed between the first connection electrode and the second connection electrode, and a first group of opposite edges includes: an edge, close to the first gap, of the first connection electrode; and an edge, close to the first gap, of the second connection electrode; a second group of opposite edges includes: an edge, far away from the first gap, of the first connection electrode; and an edge, far away from the first gap, of the second connection electrode.

Abstract: A gate driving circuit unit, a gate driving circuit and a display device are provided. The gate driving circuit unit includes a pull-up node noise-reduction circuit and a pull-up control circuit. The pull-up node noise-reduction circuit is electrically connected to an input end, a pull-down node and a pull-up node, and configured to control the pull-up node to be electrically connected to, or electrically disconnected from, the input end under the control of a potential at the pull-down node. The pull-up control circuit is electrically connected to the pull-up node and the input end, and configured to control the pull-up node to be electrically connected to the input end at an input stage.

Abstract: A biochip and a method for manufacturing the same are provided. The biochip includes: a guide layer; a channel layer on the guide layer, wherein the channel layer has therein a plurality of first channels extending in a first direction; a plurality of second channels extending in a second direction, wherein each of the plurality of second channels is in communication with the plurality of first channels, the plurality of second channels are in a layer where the channel layer is located, or in a layer where the channel layer and the guide layer are located; an encapsulation cover plate on a side of the channel layer distal to the guide layer; and a driving unit configured to drive biomolecules to move.

Abstract: Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.

Abstract: The present disclosure relates to a thin film transistor and a manufacturing method thereof. The thin film transistor includes a substrate, a first semiconductor layer, a gate dielectric layer, and a gate electrode sequentially stacked on the substrate, the first semiconductor layer has a first portion located in a channel region of the thin film transistor and a second portion in source/drain regions of the thin film transistor and located on both sides of the first portion, the second portion and first sub-portions of the first portion adjacent to the second portion include an amorphous semiconductor material, a second sub-portion of the first portion between the first sub-portions includes a polycrystalline semiconductor material, and a second semiconductor layer located in the source/drain regions and in contact with the second portion, wherein a conductivity of the second semiconductor layer is higher than a conductivity of the amorphous semiconductor material.

Abstract: A film patterning method, an array substrate, and a manufacturing method of an array substrate are disclosed. The film patterning method includes: applying photoresist on a film to be patterned; performing exposure and development on the photoresist, a region corresponding to a completely removed portion of the photoresist after the exposure and the development being a first region; post-baking the photoresist, so that the photoresist is melted and collapsed to change the region corresponding to the completely removed portion into a second region, the photoresist after post-baking forms into a mask pattern; and patterning the film by using the mask pattern as a mask.

Abstract: An embodiment of the present disclosure provides a light emitting diode chip, including: a light emitting functional layer including a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked, and a second semiconductor layer including a plurality of second semiconductor patterns which are arranged at intervals; a first electrode layer including a first electrode pattern electrically coupled to the first semiconductor layer; a second electrode layer disposed on a side, away from the light emitting layer, of the second semiconductor layer and including a plurality of second electrode patterns in one-to-one correspondence with the second semiconductor patterns, and the second electrode patterns are electrically coupled to the second semiconductor patterns correspondingly. Embodiments of the present disclosure further provide a method for manufacturing a light emitting diode chip and a display device.