Patents by Inventor Guo Cheng

Guo Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160278005
    Abstract: A data transmission system includes a device and a base. The base includes a near field communication (NFC) module and a processing module configured to determine whether a wireless network exits. The NFC module includes a determining unit configured to determine whether the NFC module writes a predetermined tag after the processing module determines the wireless network exits and configured to determine whether the predetermined tag is an authorization code, a sending unit configured to send a service set identifier (SSID) and a password to the device after the predetermined tag is the authorization code, and a control unit configured to switch an input mode of the base to a wireless network mode after the SSID and the password are sent to the device. The device is configured to be connected to the wireless network after receiving the SSID and the password. A communication method is also provided.
    Type: Application
    Filed: May 19, 2015
    Publication date: September 22, 2016
    Inventors: CHI-KANG CHIANG, WEI-TING LIN, RU-ME NA JIANG, AI-GUO CHENG, KO-YI LEE, PING-CHUAN TSAI, JING-HU SONG, SHUO-HSIU CHANG
  • Patent number: 9437565
    Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 6, 2016
    Assignee: ADVANCED SEMINCONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Chia-Ching Chen, Yi-Chuan Ding
  • Publication number: 20160190079
    Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.
    Type: Application
    Filed: December 30, 2014
    Publication date: June 30, 2016
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng LIAO, Chia-Ching CHEN, Yi-Chuan DING
  • Publication number: 20150263409
    Abstract: A smart meter capable of performing wireless transmission is used to show some power information, in which the smart meter includes an inner cylindrical case, a ring layer, an inner-layer antenna, and an outer-layer antenna. The interior of the inner cylindrical case is hollow. The ring layer surrounds the inner cylindrical case. The inner-layer antenna is attached to the ring layer and slides on the ring layer. The outer-layer antenna is also attached to the ring layer and overlaps as well as contacts with the inner-layer antenna. The inner-layer antenna and the outer-layer antenna are driven to adjust a total length of them in order to receive signals of different frequency bands.
    Type: Application
    Filed: May 19, 2014
    Publication date: September 17, 2015
    Applicant: Wistron NeWeb Corporation
    Inventors: Jiun-Kai Tseng, Ching-Chih Chien, Chia-Hong Lin, Guo-Cheng Tsai
  • Patent number: 9117697
    Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: August 25, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Che Lee, Yuan-Chang Su, Wen-Chi Cheng, Guo-Cheng Liao, Yi-Chuan Ding
  • Publication number: 20150002349
    Abstract: A radio-frequency device for a wireless communication device includes an antenna disposition area; a plurality of linearly polarized antennas for transmitting and receiving a plurality of radio signals, wherein the plurality of linearly polarized antennas are substantially disposed in the antenna disposition area in a manner such that polarization directions of the plurality of linearly polarized antennas are orthogonal to each other; and a grounding resonant element coupled to a grounding terminal of one of the plurality of linearly polarized antennas for enhancing isolations of the plurality of linearly polarized antennas.
    Type: Application
    Filed: May 4, 2014
    Publication date: January 1, 2015
    Applicant: Wistron NeWeb Corporation
    Inventors: Yen-Chun Peng, Yen-Liang Wu, Cheng-Geng Jan, Guo-Cheng Tsai, Huang-Tse Peng, Chin-Jui Wu
  • Publication number: 20140367837
    Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 18, 2014
    Inventors: Chun-Che LEE, Yuan-Chang SU, Wen-Chi CHENG, Guo-Cheng LIAO, Yi-Chuan DING
  • Publication number: 20140118202
    Abstract: A smart electric meter is provided. The smart electric meter includes a body, an antenna holder, an antenna structure and a supporting member. The antenna holder is disposed on the body, wherein the antenna holder is annular. The antenna structure is disposed on the antenna holder, wherein the antenna structure is moveable along a circumferential direction of the antenna holder. The supporting member is connected to the antenna structure, wherein the supporting member is moveably disposed on the antenna holder, and the supporting member moves the antenna structure along the circumferential direction of the antenna holder.
    Type: Application
    Filed: August 14, 2013
    Publication date: May 1, 2014
    Applicant: Wistron NeWeb Corp.
    Inventors: Chia-Hong LIN, Chang-Hsiu HUANG, I-Shan CHEN, Guo-Cheng TSAI, Chun-Chia KUO
  • Publication number: 20140001621
    Abstract: A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.
    Type: Application
    Filed: August 26, 2013
    Publication date: January 2, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Guo-Cheng Liao
  • Patent number: 8531017
    Abstract: A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: September 10, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Guo-Cheng Liao
  • Publication number: 20120061808
    Abstract: A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.
    Type: Application
    Filed: February 14, 2011
    Publication date: March 15, 2012
    Inventor: Guo-Cheng Liao
  • Patent number: 8115104
    Abstract: A circuit board with a buried conductive trace formed thereon according to the present invention is provided. A buried conductive trace layer is formed on the surface of a substrate and the pads and fingers of the conductive trace layer are heightened to facilitate the subsequent process of molding.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: February 14, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Guo Cheng Liao
  • Patent number: 7999389
    Abstract: A via hole structure and a manufacturing method thereof are provided. The via hole structure is disposed on a substrate. The substrate has a through hole, which passes through the substrate from a top surface to a bottom surface. The via hole structure comprises a conductive layer, several first conductive lines and several second conductive lines. The conductive layer having several conductive sections is disposed on the inner wall of the through hole. The first conductive lines are adjacent to the top surface for connecting the top ends of the conductive sections. The second conductive lines are adjacent to the bottom surface for connecting the bottom ends of the conductive sections. The conductive sections, the first conductive lines and the second conductive lines are serially connected to form a three-dimension layout.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: August 16, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Guo-Cheng Liao
  • Patent number: 7994429
    Abstract: A manufacturing method and structure for substrate with vertically embedded capacitors includes the steps of providing a plurality of conductive layers having a first dielectric layer and a leading wire layer formed on the first dielectric layer, providing a plurality of composite layers having a second dielectric layer and a patterned electrode layer formed on the second dielectric layer, laminating the conductive layers and the composite layers to form a block which defines a plurality of substrates with vertically embedded capacitors and a plurality of sawing streets between the substrates, and sawing the block along the sawing streets to singularize the substrates.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: August 9, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Guo-Cheng Liao
  • Patent number: 7816608
    Abstract: A substrate for inspecting a thickness of contacts at least includes a dielectric layer, a first metal layer, and a second metal layer. The first metal layer which includes a circuit region and a testing region is formed on an upper surface of the dielectric layer, and the circuit region has a plurality of contacts. The second metal layer which has a hollowed region is formed on a lower surface of the dielectric layer, and the hollowed region is aligned with the testing region of the first metal layer to avoid the interference when the testing region is inspected.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: October 19, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.,
    Inventor: Guo-Cheng Liao
  • Patent number: 7763982
    Abstract: A package substrate strip having a reserved plating bar and a metal surface treatment method thereof are provided. The metal surface treatment method forms a conductive layer connecting the reserved plating bar and bonding pads of the package substrate stripe and further forms an isolating layer covering the conductive layer. By original plating bars and the reserved plating bar, an anti-oxidation layer can be simultaneously formed on finger contacts, first ball pads electrically connected to the finger contacts, and second ball pads electrically connected to the bonding pads. The package substrate strip and the method for metal surface treatment thereof can simplify manufacturing process, reduce production cost, and improve production efficiency and yield. Furthermore, a chip package applying the package substrate strip is also provided.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: July 27, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Guo-cheng Liao
  • Publication number: 20100142796
    Abstract: An inspection method and apparatus for a substrate are provided. The inspection apparatus includes an optical unit generating a light illuminating the substrate to generate an image, a sensor array receiving the image having a light wave comprising a wave-band within a range between 700 nm to 1500 nm, and an image processing unit capturing the image.
    Type: Application
    Filed: December 5, 2008
    Publication date: June 10, 2010
    Inventors: Jen-Ming Chang, Mau-Hsiung Hsu, Yen-Hsin Tseng, Guo-Cheng Ho, Hsuan Yang, Chih-Chieh Yu, Jia-Lin Shen, Jui-Yu Lin
  • Publication number: 20090308647
    Abstract: A circuit board with a buried conductive trace formed thereon according to the present invention is provided. A buried conductive trace layer is formed on the surface of a substrate and the pads and fingers of the conductive trace layer are heightened to facilitate the subsequent process of molding.
    Type: Application
    Filed: May 28, 2009
    Publication date: December 17, 2009
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Guo Cheng LIAO
  • Publication number: 20090288861
    Abstract: A circuit board with a buried conductive trace formed thereon according to the present invention is provided. A buried conductive trace layer is formed on the surface of a substrate and the pads of the conductive trace layer are plated with a layer of copper so that the pads are heightened to facilitate the subsequent process of molding.
    Type: Application
    Filed: April 13, 2009
    Publication date: November 26, 2009
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Guo Cheng LIAO
  • Patent number: D618896
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: July 6, 2010
    Assignee: Payless ShoeSource Worldwide, Inc.
    Inventors: Robert L. Elliott, Steven C. Waugh, Tsun-Mu Tseng, I-Chang Lee, Guo Cheng Huang