Patents by Inventor Guobiao Zhang

Guobiao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Double-biased three-dimensional one-time-programmable memory
    Patent number: 10706945
    Abstract: A double-biased three-dimensional one-time-programmable read-only memory (3D-OTP) comprises an OTP array stacked on a semiconductor substrate. The OTP array comprises a dummy word line, a plurality of data word lines and data bit lines. The dummy OTP cells at the intersections of the dummy word line and all data bit lines are unprogrammed. During read, both voltages on the dummy word line and a selected data word line are raised.
    Type: Grant
    Filed: September 9, 2018
    Date of Patent: July 7, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Positioning method using music pieces
    Patent number: 10704913
    Abstract: A positioning method using music pieces continuously provides positioning service. At each signature burst (i.e., a highly unique short musical segment suitable for positioning), sounds of a music piece are used for positioning. Between signature bursts, dead reckoning (DR) is used.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 7, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Configurable computing array
    Patent number: 10700686
    Abstract: A configurable computing array comprises at least an array of configurable interconnects, at least an array of configurable logic elements and at least an array of configurable computing elements. Each configurable computing element comprises at least a programmable memory for storing a look-up table (LUT) for a math function.
    Type: Grant
    Filed: November 11, 2018
    Date of Patent: June 30, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Discrete Three-Dimensional Processor
    Publication number: 20200185371
    Abstract: A discrete 3-D processor comprises first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.
    Type: Application
    Filed: January 16, 2019
    Publication date: June 11, 2020
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable Processor
    Publication number: 20200127665
    Abstract: A configurable processor comprises at least an array of configurable computing elements (CCE's). Each CCE comprises at least a three-dimensional (3-D) memory (3D-M) array; an arithmetic logic circuit (ALC); and, a plurality of inter-storage-processor (ISP) connections. Not penetrating through any semiconductor substrate, the ISP-connections are short, small and numerous.
    Type: Application
    Filed: November 24, 2019
    Publication date: April 23, 2020
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Shared Three-Dimensional Vertical Memory
    Publication number: 20200091232
    Abstract: In a shared three-dimensional vertical memory (3D-MV), each horizontal address line comprises at least two regions: a lightly-doped region and a low-resistivity region. The lightly-doped region is formed around selected memory holes and shared by a plurality of low-leakage memory cells. The low-resistivity region forms a conductive network to reduce the resistance of the horizontal address line.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Three-dimensional one-time-programmable memory with a dummy word line
    Patent number: 10580507
    Abstract: To reduce the pre-programming cost, an efficient three-dimensional one-time-programmable read-only memory (3D-OTP) is disclosed. It comprises a dummy word line and a plurality of dummy bit lines. Only the dummy OTP cells at the intersections of the dummy word line and dummy bit lines are programmed. All other dummy OTP cells are unprogrammed.
    Type: Grant
    Filed: September 9, 2018
    Date of Patent: March 3, 2020
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Three-dimensional one-time-programmable memory comprising dummy bit lines
    Patent number: 10573399
    Abstract: A multi-bit-per-cell three-dimensional read-only memory (3D-OTPMB) comprises a plurality of dummy bit lines. It comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP array comprises at least four dummy bit lines.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: February 25, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Coordinated parking-monitoring system
    Patent number: 10574903
    Abstract: A coordinated parking-monitoring system comprises a plurality of camera-based parking-monitoring devices. Each camera in the coordinated parking-monitoring system can effectively monitor more parking areas than a single camera-based parking-monitoring device.
    Type: Grant
    Filed: September 8, 2019
    Date of Patent: February 25, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: WenSheng Wang, Guobiao Zhang
  • Three-dimensional vertical memory
    Patent number: 10566388
    Abstract: In a shared three-dimensional vertical memory (3D-MV), each horizontal address line comprises at least two regions: a lightly-doped region and a low-resistivity region. The lightly-doped region is formed around selected memory holes and shared by a plurality of low-leakage memory cells. The low-resistivity region forms a conductive network to reduce the resistance of the horizontal address line.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: February 18, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Shared infrared (IR) bicycle and methods
    Patent number: 10562580
    Abstract: A preferred IR-bicycle comprises an infrared (IR) sensor and non-IR electronics. The IR sensor detects a person in the proximity of the IR-bicycle (i.e. a nearby person). Once the IR sensor detects a nearby person, the non-IR electronics switches from a first mode to a second mode, wherein the power consumption in the first mode is substantially lower than that in the second mode.
    Type: Grant
    Filed: September 8, 2019
    Date of Patent: February 18, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao Zhang, Chuan Tang
  • Pattern Processor
    Publication number: 20200050565
    Abstract: To achieve a better overall performance, a preferred pattern processor offsets large latency with massive parallelism. The preferred pattern processor could be either a pattern-processor die comprising 3-D non-volatile memory (3D-NVM) arrays, or a pattern-processor doublet comprising a 3D-NVM die and a pattern-processing die bonded face-to-face. A searchable storage comprises a plurality of storage-like pattern processors, each of which not only stores data but also has in-situ searching capabilities.
    Type: Application
    Filed: October 7, 2019
    Publication date: February 13, 2020
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Three-dimensional vertical one-time-programmable memory comprising Schottky diodes
    Patent number: 10559574
    Abstract: The present invention discloses a three-dimensional vertical read-only memory (3D-OTPV) comprising Schottky diodes. It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string is vertical to the substrate and comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. A plurality of Schottky diodes are formed between the horizontal address lines and the vertical address lines.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: February 11, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Processor for enhancing network security
    Patent number: 10560475
    Abstract: The present invention discloses a processor for enhancing network security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing rule/virus patterns and a pattern-processing circuit for performing pattern processing on an incoming network packet against said rule/virus patterns. The 3D-M array is stacked above the pattern-processing circuit.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: February 11, 2020
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Coordinated Parking-Monitoring System
    Publication number: 20200036907
    Abstract: A coordinated parking-monitoring system comprises a plurality of camera-based parking-monitoring devices. Each camera in the coordinated parking-monitoring system can effectively monitor more parking areas than a single camera-based parking-monitoring device.
    Type: Application
    Filed: September 8, 2019
    Publication date: January 30, 2020
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: WenSheng WANG, Guobiao ZHANG
  • Processor For Enhancing Network Security
    Publication number: 20200036733
    Abstract: To achieve a better overall performance, a preferred pattern processor offsets large latency with massive parallelism. It comprises a plurality of storage-processing units (SPU's), each of which comprises a single pattern-processing circuit, at least a three-dimensional memory (3D-M) array and a plurality of inter-storage-processor (ISP) connections. The ISP-connections do not penetrate through any semiconductor substrate.
    Type: Application
    Filed: October 6, 2019
    Publication date: January 30, 2020
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Shared Infrared (IR) Bicycle and Methods
    Publication number: 20190389527
    Abstract: A preferred IR-bicycle comprises an infrared (IR) sensor and non-IR electronics. The IR sensor detects a person in the proximity of the IR-bicycle (i.e. a nearby person). Once the IR sensor detects a nearby person, the non-IR electronics switches from a first mode to a second mode, wherein the power consumption in the first mode is substantially lower than that in the second mode.
    Type: Application
    Filed: September 8, 2019
    Publication date: December 26, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao ZHANG, Chuan TANG
  • Detecting Method for Front-Parked Vehicles At Night
    Publication number: 20190389380
    Abstract: To detect front-parked vehicles at night (i.e. a vehicle is parked with its head facing the inside of a parking space), a detection device uses the light beam from a passing-by vehicle to extract at least a reflection of at least a tail light or at least a portion of a back bumper from an image captured for a parking space.
    Type: Application
    Filed: September 8, 2019
    Publication date: December 26, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Searchable Storage
    Publication number: 20190370465
    Abstract: To achieve a better overall performance, a preferred pattern processor based on 3-D memory offsets large latency with massive parallelism. A searchable storage comprises a plurality of searchable 3-D memory dice, each of which has in-situ searching capabilities.
    Type: Application
    Filed: August 17, 2019
    Publication date: December 5, 2019
    Inventor: Guobiao ZHANG
  • Three-Dimensional Vertical Memory
    Publication number: 20190363132
    Abstract: In a shared three-dimensional vertical memory (3D-Mv), each horizontal address line comprises at least two regions: a lightly-doped region and a low-resistivity region. The lightly-doped region is formed around selected memory holes and shared by a plurality of low-leakage memory cells. The low-resistivity region forms a conductive network to reduce the resistance of the horizontal address line.
    Type: Application
    Filed: September 20, 2018
    Publication date: November 28, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG